Interview-style puzzles about UVM as it is used in real testbenches: phase order and objections, the factory and uvm_config_db, sequences and sequencers, and scoreboards, analysis ports and the register layer. All answers assume UVM 1.2 and state where 1.1d differs. Because the UVM library is not installed in the course tooling, each runnable check is a small hand-written plain-SystemVerilog model of the documented mechanism, and the others say why they could not be run.
UVM Phases and Objections — 6 puzzles
Factory and config_db — 6 puzzles
Sequences and Sequencers — 6 puzzles
Analysis, Scoreboards and RAL — 6 puzzlesOpen each topic and attempt every puzzle cold, writing your predicted answer first.
Only then read the step-by-step solution and confirm the exact answer.
Re-read the 'why candidates get it wrong' note — that is the actual interview signal.
Finish with the section Q&A to rehearse explaining the rule out loud.