Difficulty: Hard · Puzzle 3 of 6 · Topic: Analysis, Scoreboards and RAL
UVM 1.2. A register model is used by master M0 through its adapter; a second master M1 writes the same register directly (not through the model). Three environments differ only in prediction. All do: model write of 5 through M0, then M1 writes 7 on the bus. Setup A: default settings (no auto-predict, no predictor). Setup B: `map.set_auto_predict(1)`, no predictor. Setup C: auto-predict off, a uvm_reg_predictor connected to a bus monitor that sees all traffic. What is the mirror value at the end in A, B and C?
// Setup A (defaults): nothing extra
// Setup B
rm.default_map.set_auto_predict(1);
// Setup C (connect_phase)
predictor.map = rm.default_map;
predictor.adapter = adapter;
bus_mon.ap.connect(predictor.bus_in); // monitors the shared bus: M0 and M1 traffic
// all setups, in the sequence
rm.ctrl.write(status, 5); // through M0
// M1 then writes 7 to the same register on the bus (outside the model)Ask for each setup: what is the only thing that ever tells the mirror about a bus access?
1) A: auto-predict is off by default and there is no predictor, so nothing ever updates the mirror: after both writes it still holds the reset value (0), while the DUT holds 7.
2) B: the model's own write updates the mirror at once (5), but M1's write goes around the model and nothing observes it: the mirror stays 5 and is stale (DUT 7).
3) C: the predictor sees every transaction on the bus, M0's 5 and M1's 7, converts them with the adapter and updates the mirror: it ends at 7, matching the DUT.
4) Rule: use auto-predict only when the model is the sole bus master; as soon as other masters (or a DUT-internal writer) exist, use an explicit predictor on a monitor that sees all traffic and leave auto-predict off.Answer: A: 0 (never updated). B: 5 (stale after M1). C: 7 (correct).
Checked by running the code in Verilator 5; the printed output supports the answer above. Hand-written model of the documented UVM 1.2 behaviour in plain SystemVerilog (Verilator), not the UVM library: a register with a DUT value and a mirror, updated only by auto-predict (model writes) or an explicit predictor (every bus access).
Default is auto-predict off: a front-door write through the model does not touch the mirror unless auto-predict or a predictor does it, so a later `mirror(UVM_CHECK)` reports a mismatch that is a testbench error, not a DUT bug.
What goes wrong if the predictor is connected AND auto-predict is on? Model answer: the mirror is updated twice for the model's own accesses (once directly, once by the predictor); for plain registers this is harmless, but it makes the flow hard to reason about for volatile and clear-on-read fields, so pick one mechanism per map.