Difficulty: Easy · Puzzle 4 of 6 · Topic: Analysis, Scoreboards and RAL
UVM 1.2, register with reset value 0, auto-predict on. After `set(5)`, what do get() and get_mirrored_value() return, and what is on the DUT? After `update()`? After `predict(9)`?
rg.set(5);
`uvm_info("R", $sformatf("desired=%0d mirror=%0d", rg.get(), rg.get_mirrored_value()), UVM_LOW)
rg.update(status);
`uvm_info("R", $sformatf("desired=%0d mirror=%0d", rg.get(), rg.get_mirrored_value()), UVM_LOW)
void'(rg.predict(9));
`uvm_info("R", $sformatf("desired=%0d mirror=%0d", rg.get(), rg.get_mirrored_value()), UVM_LOW)Which of set, update and predict touch the bus, and which of the two model values does each change?
1) set(5) changes only the desired value: desired=5, mirror=0, DUT still 0, no bus access.
2) update() writes the register over the bus when desired differs from the mirror; with auto-predict the mirror follows: desired=5, mirror=5, DUT=5.
3) predict(9) changes the model values with no bus access, setting both the mirror and the desired value to 9: desired=9, mirror=9, DUT is still 5 (the model now deliberately disagrees with the DUT).Answer: After set: desired 5, mirror 0, DUT 0. After update: 5, 5, DUT 5. After predict(9): desired 9, mirror 9, DUT 5.
Checked by running the code in Verilator 5; the printed output supports the answer above. Hand-written model of the documented UVM 1.2 behaviour in plain SystemVerilog (Verilator), not the UVM library: a register with three values (desired, mirror, DUT) and the three operations.
predict() makes the model say 9 without telling the DUT, so a subsequent mirror(UVM_CHECK) reports a mismatch; it is for recording what the bus did (predictors), not for writing.
When would update() do nothing? Model answer: when desired already equals the mirror for every field; update() writes only registers whose desired value differs from the mirror, so calling set() with the current value is a no-op for the bus.