Day 1

SystemVerilog Language Puzzles; OOP & Testbench Puzzles

datatype-and-bit-puzzles-2: Signed vs Unsigned Comparison Trap (M); fork-join-puzzles-1: join vs join_any vs join_none (E); fork-join-puzzles-2: Loop Variable Capture in Detached Threads (M); string-and-casting-puzzles-4: Enum Safety with $cast (M) | handle-and-copy-puzzles-1: Shallow Copy in Nested Payload (E); virtual-method-puzzles-1: Non-Virtual vs Virtual Through Base Handle (E); parameterized-class-puzzles-1: Global Static vs Per-Specialization Static (E); factory-override-puzzles-1: Type Override vs Instance Override Precedence (M)

Attempt cold with the timer, score 0 to 4, say each answer out loud once.

Day 2

Concurrency & Timing Puzzles; Randomization & Constraint Puzzles

event-scheduling-puzzles-2: Does #0 Beat NBA? (E); race-condition-puzzles-3: Reading q Before the NBA (Not a Race) (E); clocking-block-puzzles-1: Why Every Sample Is One Cycle Old (M); semaphore-mailbox-puzzles-2: Bounded Mailbox put Deadlock (M) | constraint-order-02-bidirectional-sum: Bidirectional Solving of x+y==10 (E); dist-02-range-cardinality-skew: Small Range with := vs Large Range with :/ (E); solve-before-01-classic-a-b: Classic a->b Bias Shift (E); randomize-with-04-constraint-mode-toggle: constraint_mode Changes Pass/Fail (E)

Attempt cold with the timer, score 0 to 4, say each answer out loud once.

Day 3

SVA Assertion Puzzles; Functional Coverage Puzzles

imp-001: Overlap vs Non-Overlap (E); imp-002: Pure Vacuity (E); temp-003: $fell Is an Event, Not a Level (E); dbg-001: disable iff Reset Glitch Hides a Lost Grant (M) | cov-cg-002: Default bin is not scored (E); cov-cross-002: Pure auto cross count (E); cov-opt-003: Instance coverage, type coverage and merge_instances (M); cov-close-002: Unreachable bin from stimulus constraints (E)

Attempt cold with the timer, score 0 to 4, say each answer out loud once.

Day 4

Logic & Aptitude Puzzles; Scenario & Debug Puzzles

classic-01: 9 Balls, 1 Heavier, 2 Weighings (E); probability-03: Two Children, At Least One Boy (E); logic-02: One-Cycle Pulse Across Clock Domains (M) | tb-001: Handshake Hang: Missing item_done on One Branch (M); dead-001: Early Return Leaves Objection Raised (E); sb-001: Out-of-Order Responses Miscompared as Corruption (M); sb-003: Duplicate Transactions from Handle Reuse (E)

Attempt cold with the timer, score 0 to 4, say each answer out loud once.

Day 5

UVM Testbench Puzzles; Clock, Reset & CDC Puzzles; Bus and Interface Protocol Puzzles

uvm-phase-01: Which Way Do the Phases Walk the Tree (E); uvm-config-01: Virtual Interface Set with a Relative Path from Top (E); uvm-seq-05: Virtual Sequence Started With null (E); uvm-sb-04: Desired, Mirrored and update() (E) | crc-rst-01: A Reset Pulse Between Two Clock Edges (E); crc-clk-02: A Latch Makes the Gate Safe (E); crc-cdc-03: Why Gray Code Across Clock Domains (E); crc-ver-01: RTL Simulation Cannot Tell One Flop From Two (E) | proto-hs-01: Counting Transfers in a Valid/Ready Trace (E); proto-apb-01: Setup, Access and Completed Transfers (E); proto-axi-01: The 4 KB Rule Splits a Burst (E)

Attempt cold with the timer, score 0 to 4, say each answer out loud once.

Day 6

Interview prep

Framework for any unseen puzzle; Testbench Hang; Constraint No-Solution; Vacuous Assertion Pass

Read the framework, then talk through two live-interview pages out loud.

Day 7

Cheatsheet and re-do

Cheatsheet; Interview-day tips; Coverage Not Closing; Race That Only Shows on Silicon-Like Gate-Level Timing; Coverage Closed at 100 Percent but a Bug Escaped

Re-do every puzzle you scored 2 or lower this week, cold, with the timer. Stop early the night before.