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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
    • Valid/Ready Handshake Puzzles
    • APB Protocol Puzzles
    • AXI Protocol Puzzles
      • The 4 KB Rule Splits a Burst
      • OKAY, SLVERR or DECERR?
      • WRAP Burst Address Sequence
      • WLAST One Beat Early
      • How Many Read Orders Are Legal?
      • Whose Data Is This? W Has No ID
    • FIFO, Arbitration and Credit Puzzles
    • Bus and Interface Protocol Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←AXI Protocol Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Bus and Interface Protocol Puzzles
  4. AXI Protocol Puzzles
  5. The 4 KB Rule Splits a Burst
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    VLSI DV Interview PuzzlesAll levels

    The 4 KB Rule Splits a Burst

    AXI4. A master wants one INCR write of 32 beats of 4 bytes starting at 0x0FC0. Is it legal? If not, split it into the fewest legal bursts: give each burst's address and AWLEN. (The Python run applies the AXI4 address rules to confirm the split.)

    Puzzle

    Difficulty: Easy · Puzzle 1 of 6 · Topic: AXI Protocol Puzzles

    AXI4. A master wants one INCR write of 32 beats of 4 bytes starting at 0x0FC0. Is it legal? If not, split it into the fewest legal bursts: give each burst's address and AWLEN. (The Python run applies the AXI4 address rules to confirm the split.)

    Code

    design.sv
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    // AXI4 write address channel request
    AWADDR  = 32'h0000_0FC0;
    AWBURST = 2'b01;        // INCR
    AWSIZE  = 3'd2;         // 4 bytes per beat
    AWLEN   = 8'd31;        // 32 beats

    Hint

    Total size is 128 bytes. How many bytes remain until the next 4 KB boundary at 0x1000?

    Step-by-step solution

    Diagram
    1) 32 beats x 4 bytes = 128 bytes, so the burst covers 0x0FC0 to 0x103F.
    2) It crosses the 4 KB boundary at 0x1000 -> illegal (a burst must never cross a 4 KB boundary).
    3) Bytes before the boundary: 0x1000 - 0x0FC0 = 0x40 = 64 bytes = 16 beats.
    4) Burst 1: address 0x0FC0, 16 beats, AWLEN=15. Burst 2: address 0x1000, the remaining 16 beats, AWLEN=15.

    Answer

    Answer: Illegal as issued. Split into two INCR bursts: 0x0FC0 with AWLEN=15 and 0x1000 with AWLEN=15.

    How this was checked

    Checked by running a model of the rule in a Python model. A Python model of the AXI4 address rules (first beat may be unaligned, later beats are size-aligned) checks the split and the unaligned follow-up.

    Why candidates get it wrong

    AWLEN=31 is well inside the 256-beat INCR limit, so the length alone looks fine. The rule is about the address range, so a generator that only constrains AWLEN <= 255 produces illegal bursts whenever the start address is close enough to a 4 KB boundary; and the fix is to split, not to clamp the length at a fixed 16.

    Interviewer follow-up

    For INCR with AWADDR=0x1F2C, AWSIZE=3 (8 bytes per beat), what is the largest legal AWLEN? Model answer: 26 (27 beats). The first beat transfers only 4 bytes up to the aligned address 0x1F30, then 26 aligned 8-byte beats end exactly at 0x1FFF; AWLEN=27 would cross 0x2000.

    Related topics

    • Back to AXI Protocol Puzzles

    • Bus and Interface Protocol Puzzles section

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    See also

    • WRAP Burst Address Sequence
    • WLAST One Beat Early
    • How Many Read Orders Are Legal?