Difficulty: Medium · Puzzle 5 of 6 · Topic: AXI Protocol Puzzles
AXI4 master issues three single-beat reads in this order: A (ARID=0), B (ARID=1), C (ARID=0). The slave side may return data in any order the protocol permits. Of the six possible return orders of A, B, C, how many are legal?
`timescale 1ns/1ns
module tb;
// Reads issued in this order on one master: A (ARID 0), B (ARID 1), C (ARID 0).
typedef struct { string name; int id; } rd_t;
rd_t issued[3] = '{ '{"A", 0}, '{"B", 1}, '{"C", 0} };
int legal = 0;
// Check one candidate return order (indices into issued[]).
task automatic check(int o0, int o1, int o2);
int order[3] = '{o0, o1, o2};
int next_idx[2] = '{0, 0}; // per ARID: position of the next response it must return
string seq = "";
bit ok = 1;
foreach (order[k]) begin
int id = issued[order[k]].id;
int pos = 0, want = -1;
// the next outstanding read of this ID, in issue order
foreach (issued[j]) if (issued[j].id == id) begin
if (pos == next_idx[id]) want = j;
pos++;
end
if (want != order[k]) ok = 0;
next_idx[id]++;
seq = {seq, issued[order[k]].name};
end
if (ok) legal++;
if (ok) $display("return order %s : LEGAL", seq);
else $display("return order %s : ILLEGAL (same-ID reads returned out of order)", seq);
endtask
initial begin
check(0,1,2); check(0,2,1); check(1,0,2);
check(1,2,0); check(2,0,1); check(2,1,0);
$display("legal orders = %0d of 6", legal);
#1 $finish;
end
endmoduleWhich reads share an ID? Responses with the same ID must come back in request order; different IDs have no ordering constraint.
1) A and C share ARID=0, so A must return before C. B (ARID=1) is unconstrained.
2) List the six orders: ABC, ACB, BAC are legal (A before C). BCA, CAB, CBA return C before A and are illegal.
3) Legal orders: 3 of 6.Answer: 3 of 6: ABC, ACB and BAC. B may appear anywhere; A must precede C.
Checked by running the code in Verilator 5; the printed output supports the answer above. A per-ID queue checker enumerates all six return orders and accepts exactly the ones with A before C.
Two common wrong answers: 6 ('AXI allows out-of-order, so anything goes') and 1 ('responses must stay in issue order'). The ordering rule is per ID, not global. Also notice that a monitor must track ordering per ID: a single global queue gives false errors on BAC and ACB.
If A and C use the same ID but are sent to a slow DDR and a fast SRAM, who guarantees A comes back first? Model answer: The interconnect. It must hold C's response until A's has returned (or stall issuing C to a different slave while A is outstanding), because a slave cannot know about the other slave's transaction.