Difficulty: Medium · Puzzle 4 of 6 · Topic: AXI Protocol Puzzles
Burst A is announced with AWLEN=2 (3 beats), burst B with AWLEN=1 (2 beats). The master drives four W beats in the cycles below: WLAST pattern 0, 1, 0, 1. A monitor expects WLAST exactly on the last beat of each burst (counting beats from AWLEN). What does it report, and what is the root cause?
`timescale 1ns/1ns
module tb;
localparam int N = 4;
int awlen_q[$] = '{2, 1}; // burst A has 3 beats, burst B has 2 beats
// W beat: 0123
localparam bit [0:N-1] WLAST = 4'b0101; // the master gave burst A only two beats
bit clk = 0;
int cyc = 0, idx = 0, bad = 0, cur_len = -1;
always #5 clk = ~clk;
wire wvalid = 1, wlast = WLAST[cyc];
always @(posedge clk) begin
bit expect_last;
if (cur_len < 0) cur_len = awlen_q.pop_front(); // next burst's AWLEN
expect_last = (idx == cur_len);
if (wlast !== expect_last) begin
bad++;
$display("WLAST ERROR W-beat %0d (index %0d of AWLEN=%0d): WLAST=%0b expected %0b", cyc, idx, cur_len, wlast, expect_last);
end else $display("W-beat %0d ok (index %0d of AWLEN=%0d, WLAST=%0b)", cyc, idx, cur_len, wlast);
if (idx == cur_len) begin idx = 0; cur_len = -1; end else idx++;
if (cyc == N-1) $display("errors = %0d", bad);
cyc <= cyc + 1;
end
initial #(10*N) $finish;
endmoduleBeats are assigned to bursts in AW order. Track the beat index inside the current burst.
1) W beat 0: index 0 of burst A (AWLEN=2): WLAST=0 is right.
2) W beat 1: index 1 of burst A: expected WLAST=0, got 1 -> error. The master ended burst A one beat early.
3) The monitor still expects a third beat of A, so W beat 2 (really burst B's first beat) is index 2: expected WLAST=1, got 0 -> error. Burst A is now complete in the monitor.
4) W beat 3 is index 0 of burst B (AWLEN=1): expected 0, got 1 -> error.
5) Three errors, one cause: burst A got only 2 beats instead of 3. Every beat after it is mis-assigned until the monitor is resynchronised.Answer: Three WLAST errors, at W beats 1, 2 and 3; the first one is the root cause (the master sent a 2-beat burst for AWLEN=2).
Checked by running the code in Verilator 5; the printed output supports the answer above. One short burst produces a cascade of three WLAST mismatches; the first is the root cause.
Only the first error is real. Later errors are a cascade of misalignment: a short burst makes every following beat land in the wrong burst slot, so a log with three errors invites debugging the wrong beat. Also, a slave that ignores WLAST and counts AWLEN would store burst B's first beat in burst A.
Why does AXI make the master drive WLAST if the slave already knows AWLEN? Model answer: Components that do not hold the AW information at that point (interconnect W routing and arbitration, width converters, protocol checkers) rely on WLAST as the in-band marker to switch the W path to the next burst; it is also the only way to detect a short or long burst.