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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
    • Valid/Ready Handshake Puzzles
    • APB Protocol Puzzles
    • AXI Protocol Puzzles
      • The 4 KB Rule Splits a Burst
      • OKAY, SLVERR or DECERR?
      • WRAP Burst Address Sequence
      • WLAST One Beat Early
      • How Many Read Orders Are Legal?
      • Whose Data Is This? W Has No ID
    • FIFO, Arbitration and Credit Puzzles
    • Bus and Interface Protocol Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←AXI Protocol Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Bus and Interface Protocol Puzzles
  4. AXI Protocol Puzzles
  5. WRAP Burst Address Sequence
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    VLSI DV Interview PuzzlesAll levels

    WRAP Burst Address Sequence

    AXI4 WRAP burst: AWADDR=0x34, AWSIZE=2 (4 bytes), AWLEN=3. List the four beat addresses. The code also prints two more bursts (the second is a 16-byte window of 2-byte beats starting at 0x1C, the third starts exactly on the window boundary 0x30) so you can check your method.

    Puzzle

    Difficulty: Medium · Puzzle 3 of 6 · Topic: AXI Protocol Puzzles

    AXI4 WRAP burst: AWADDR=0x34, AWSIZE=2 (4 bytes), AWLEN=3. List the four beat addresses. The code also prints two more bursts (the second is a 16-byte window of 2-byte beats starting at 0x1C, the third starts exactly on the window boundary 0x30) so you can check your method.

    Code

    tb.sv
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    `timescale 1ns/1ns
    module tb;
      // AXI4 WRAP burst address sequence. nbeats must be 2, 4, 8 or 16 and start must be aligned to the beat size.
      task automatic wrap(string name, int start, int size_bytes, int nbeats);
        int total = size_bytes * nbeats;
        int lower = (start / total) * total;          // wrap boundary (lowest address of the window)
        int upper = lower + total;
        int addr  = start;
        string s = "";
        for (int i = 0; i < nbeats; i++) begin
          s = {s, $sformatf("0x%0h ", addr)};
          addr += size_bytes;
          if (addr == upper) addr = lower;
        end
        $display("%s: window 0x%0h..0x%0h : %s", name, lower, upper - 1, s);
      endtask
    
      initial begin
        wrap("A  AWLEN=3 size=4B start=0x34", 'h34, 4, 4);
        wrap("B  AWLEN=7 size=2B start=0x1C", 'h1C, 2, 8);
        wrap("C  AWLEN=3 size=4B start=0x30", 'h30, 4, 4);
        #1 $finish;
      end
    endmodule

    Hint

    The wrap window is beats x bytes long, aligned to its own size. The address wraps when it reaches the top of the window.

    Step-by-step solution

    Diagram
    1) Window size = 4 beats x 4 bytes = 16 bytes. 0x34 lies in the 16-byte-aligned window 0x30-0x3F.
    2) Beat 0: 0x34. Beat 1: 0x38. Beat 2: 0x3C.
    3) The next increment is 0x40 = top of the window, so it wraps to the lower boundary 0x30. Beat 3: 0x30.
    4) Check: burst B uses the window 0x10-0x1F: 0x1C, 0x1E, 0x10, ... ; burst C starts on the lower boundary so it never wraps: 0x30, 0x34, 0x38, 0x3C.

    Answer

    Answer: 0x34, 0x38, 0x3C, 0x30. All four beats stay inside the 16-byte window 0x30-0x3F.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. The standard AXI wrap formula (window = beats x size, aligned to itself) reproduces the three sequences.

    Why candidates get it wrong

    Continuing to 0x40 (INCR behaviour) is the usual error. The second trap is the window: it is aligned to the TOTAL burst size (16 bytes here), not to the beat size, so the lower boundary is 0x30, not 0x34.

    Interviewer follow-up

    Which AxLEN values and start alignments are legal for WRAP bursts? Model answer: AxLEN must be 1, 3, 7 or 15 (2, 4, 8 or 16 beats) and the start address must be aligned to the transfer size (AxSIZE). The window length is beats x size bytes.

    Related topics

    • Back to AXI Protocol Puzzles

    • Bus and Interface Protocol Puzzles section

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    See also

    • The 4 KB Rule Splits a Burst
    • How Many Read Orders Are Legal?
    • Whose Data Is This? W Has No ID