AMBA APB (APB3/APB4): setup and access phases, PREADY wait states, PSLVERR validity, back-to-back transfers and signal stability. The recurring trap is treating APB as pipelined or sampling a signal outside the one cycle where it is defined.
1. Setup, Access and Completed Transfers [Easy]
2. Two Wait States: Total Cycles and Write Moment [Easy]
3. When Is PSLVERR Real? [Medium]
4. Can Two Transfers Fit in Three Cycles? [Medium]
5. Write Data Changes in a Wait State [Medium]
6. Sampling PRDATA One Cycle Too Early [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
puzzle prompt
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requirements decode --> constraints/assumptions --> solve strategy
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+------------------> corner cases ---------> final answer
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explain trade-offs
Use section visuals when available; fallback preserves reasoning flow.