Difficulty: Medium · Puzzle 4 of 6 · Topic: APB Protocol Puzzles
Two zero-wait-state APB transfers back to back. A designer proposes a 3-cycle waveform: PSEL=111, PENABLE=011, PREADY=111 (second access starts right after the first). The legal alternative keeps PSEL high with PENABLE=0101 over 4 cycles. Which waveform is legal, where is the violation in the other, and what is the minimum number of cycles for two transfers?
`timescale 1ns/1ns
// Checks the legal ways PENABLE may rise: only right after a SETUP cycle, or while an ACCESS is still waiting.
module chk #(parameter string NAME = "?", parameter int N = 4,
parameter bit [0:3] PSEL = 0, parameter bit [0:3] PENABLE = 0, parameter bit [0:3] PREADY = 0)
(input bit clk);
int cyc = 0, bad = 0, done = 0;
bit p_psel = 0, p_pen = 0, p_rdy = 0;
wire psel = PSEL[cyc], penable = PENABLE[cyc], pready = PREADY[cyc];
always @(posedge clk) begin
if (penable && !( (p_psel && !p_pen) || (p_psel && p_pen && !p_rdy) )) begin
bad++;
$display("%s: VIOLATION cycle %0d: PENABLE high without a SETUP cycle first", NAME, cyc);
end
if (psel && penable && pready) done++;
p_psel <= psel; p_pen <= penable; p_rdy <= pready;
if (cyc == N-1) $display("%s: %0d transfers in %0d cycles, %0d violations", NAME, done, N, bad);
cyc <= cyc + 1;
end
endmodule
module tb;
bit clk = 0;
always #5 clk = ~clk;
// cycle: 0123
chk #("3-cycle attempt", 3, 4'b1110, 4'b0110, 4'b1110) a(clk);
chk #("4-cycle legal ", 4, 4'b1111, 4'b0101, 4'b1111) b(clk);
initial #(10*4) $finish;
endmoduleBetween two transfers PENABLE has to be low for at least one cycle: every transfer needs its own setup.
1) The 3-cycle attempt: cycle 0 SETUP, cycle 1 ACCESS completes transfer 1, cycle 2 PENABLE is high again with no SETUP before it.
2) PENABLE may be high only if the previous cycle was a SETUP or an ACCESS that is still waiting. After a completed access it must return to 0.
3) The legal waveform: cycle 0 SETUP, 1 ACCESS, 2 SETUP (PSEL stays high), 3 ACCESS. Two transfers take 4 cycles.
4) So the minimum is 4 cycles: every transfer needs one SETUP and one ACCESS cycle.Answer: The 4-cycle waveform is legal; the 3-cycle waveform violates the protocol at cycle 2 (PENABLE high with no preceding setup). Minimum = 4 cycles for two transfers (2 per transfer).
Checked by running the code in Verilator 5; the printed output supports the answer above. A setup-before-access checker rejects the 3-cycle waveform and accepts the 4-cycle one.
APB is not pipelined like AHB or AXI: there is no way to overlap the next setup with the current access. Counting the completion cycle as also the setup of the next transfer is exactly the 3-cycle mistake. PSEL may stay high between transfers, but PENABLE must fall.
Is it legal to drop PSEL between two back-to-back transfers? Model answer: Yes. PSEL may stay high (new setup immediately) or fall to idle first; both are legal. What is illegal is raising PENABLE without a setup cycle, or changing the transfer's controls while PSEL && PENABLE && !PREADY.