Difficulty: Medium · Puzzle 3 of 6 · Topic: APB Protocol Puzzles
APB4. PSLVERR is high in cycles 2, 5 and 6 of the trace below (7 cycles). A checker flags a failed transfer only where the protocol makes PSLVERR meaningful. How many transfers does it report as errors, and at which cycle?
`timescale 1ns/1ns
module tb;
localparam int N = 7;
// cycle: 0123456
localparam bit [0:N-1] PSEL = 7'b0111110;
localparam bit [0:N-1] PENABLE = 7'b0011010;
localparam bit [0:N-1] PREADY = 7'b0001010;
localparam bit [0:N-1] PSLVERR = 7'b0010011;
bit clk = 0;
int cyc = 0, n = 0, errs = 0;
always #5 clk = ~clk;
wire psel = PSEL[cyc], penable = PENABLE[cyc], pready = PREADY[cyc], pslverr = PSLVERR[cyc];
always @(posedge clk) begin
if (psel && penable && pready) begin
n++;
if (pslverr) errs++;
if (pslverr) $display("cycle %0d: transfer #%0d ERROR (PSLVERR=1)", cyc, n);
else $display("cycle %0d: transfer #%0d OKAY", cyc, n);
end
if (cyc == N-1) $display("errors = %0d of %0d transfers", errs, n);
cyc <= cyc + 1;
end
initial #(10*N) $finish;
endmoduleFind the cycles where PSEL, PENABLE and PREADY are all high, then look at PSLVERR only there.
1) PSEL=0111110, PENABLE=0011010, PREADY=0001010, PSLVERR=0010011.
2) Cycle 1: setup. Cycle 2: access with PREADY=0 -> wait state. PSLVERR=1 here is not valid yet.
3) Cycle 3: access with PREADY=1 -> transfer 1 completes with PSLVERR=0 -> OKAY.
4) Cycle 4: setup. Cycle 5: access with PREADY=1 and PSLVERR=1 -> transfer 2 completes with an error.
5) Cycle 6: PSEL=0, PSLVERR=1 is ignored.Answer: One error: transfer #2, reported at cycle 5. PSLVERR in cycle 2 (wait state) and cycle 6 (idle) is not sampled.
Checked by running the code in Verilator 5; the printed output supports the answer above. PSLVERR is sampled only at the completing access cycles 3 and 5.
PSLVERR is only considered in the last cycle of a transfer (PSEL, PENABLE and PREADY all high); the spec recommends, but does not require, driving it low otherwise. A checker that treats any high PSLVERR as an error reports 3 false failures here.
A write ends with PSLVERR=1. Can the testbench assume the register was not updated? Model answer: No. The spec says an error response does not guarantee that the register or memory kept its old value. The scoreboard should mark the target unknown or follow the specific slave's documentation, not silently model 'no change'.