Difficulty: Medium · Puzzle 2 of 6 · Topic: AXI Protocol Puzzles
System address map: 0x00000-0x0FFFF RAM (read/write), 0x10000-0x100FF status registers (read-only, the slave returns an error on writes), everything else unmapped. For the five 4-beat accesses in the code, what response does each get, who generates it, and how many R beats come back for the unmapped read?
`timescale 1ns/1ns
module tb;
typedef enum bit [1:0] {OKAY = 2'b00, SLVERR = 2'b10, DECERR = 2'b11} resp_t;
// Address map: 0x0000-0xFFFF RAM (read/write), 0x10000-0x100FF status regs (read-only), everything else unmapped
function automatic resp_t respond(bit [31:0] addr, bit is_write);
if (addr < 32'h1_0000) return OKAY;
if (addr >= 32'h1_0000 && addr < 32'h1_0100) return is_write ? SLVERR : OKAY;
return DECERR; // no slave decoded: the interconnect answers
endfunction
task automatic access(bit [31:0] addr, bit is_write, int beats);
resp_t r = respond(addr, is_write);
if (is_write) $display("WR 0x%05h : B resp = %s (one response for the whole burst)", addr, r.name());
else $display("RD 0x%05h : %0d R beats, every RRESP = %s, RLAST on beat %0d", addr, beats, r.name(), beats);
endtask
initial begin
access(32'h0_0100, 1, 4);
access(32'h1_0010, 1, 4);
access(32'h1_0010, 0, 4);
access(32'h2_0000, 1, 4);
access(32'h2_0000, 0, 4);
#1 $finish;
end
endmoduleThink about which component can answer when no slave is selected, and whether an error ends a read burst early.
1) WR 0x00100 hits RAM: OKAY.
2) WR 0x10010 reaches the read-only status block, which answers SLVERR (a slave was reached but refused the access).
3) RD 0x10010 is a legal read of that block: OKAY on every beat.
4) WR 0x20000 and RD 0x20000 hit no slave: the interconnect's default responder returns DECERR.
5) An error does not shorten a read burst: all 4 R beats return with RRESP=DECERR and RLAST on beat 4. A write gets a single B response for the whole burst.Answer: OKAY, SLVERR, OKAY, DECERR, DECERR. DECERR is generated by the interconnect (decode error, no slave); SLVERR by a slave that was reached. The unmapped 4-beat read returns 4 R beats, all DECERR, RLAST on the fourth.
Checked by running the code in Verilator 5; the printed output supports the answer above. An address-map model gives OKAY for RAM, SLVERR for a write to the read-only block, DECERR for unmapped addresses; an error read still returns every beat.
Reporting a single error beat for a failed read is wrong: the full number of R beats with RLAST must still return or the master hangs. Also 'DECERR from the slave' is wrong: DECERR normally comes from the interconnect for an address no slave decodes, not from a slave you reached.
For a 4-beat write to an unmapped address, must the interconnect still take the W beats? Model answer: Yes. It has to accept and discard all 4 W beats (through WLAST) and then return one B response with DECERR; refusing the W beats would stall the shared write-data channel and block unrelated masters.