Difficulty: Easy · Puzzle 1 of 6 · Topic: Reset Puzzles
Both flops hold 1. rst_n pulses low from t=17 to t=20, entirely between the clock edges at t=15 and t=25. Predict the three printed lines. What does this tell you about checking resets with a clocked monitor?
`timescale 1ns/1ns
module tb;
reg clk = 0, rst_n = 1, d = 1;
reg q_async, q_sync;
always #5 clk = ~clk; // posedges at 5, 15, 25, ...
always @(posedge clk or negedge rst_n)
if (!rst_n) q_async <= 1'b0; else q_async <= d;
always @(posedge clk)
if (!rst_n) q_sync <= 1'b0; else q_sync <= d;
initial begin
#17 rst_n = 0; // reset is low from 17 to 20: no clock edge inside
#1 $display("t=%0d async=%b sync=%b", $time, q_async, q_sync);
#2 rst_n = 1;
#1 $display("t=%0d async=%b sync=%b", $time, q_async, q_sync);
#5 $display("t=%0d async=%b sync=%b", $time, q_async, q_sync);
#1 $finish;
end
endmoduleWhich of the two flops needs a clock edge to notice reset?
1) Both flops load d=1 at the edge at t=5 and hold 1 afterwards.
2) q_async has negedge rst_n in its sensitivity list: the falling edge at t=17 clears it at once, so at t=18 async=0 while sync=1.
3) q_sync only looks at rst_n at a clock edge. No edge occurs between 17 and 20, so it never sees the reset at all and still shows 1 at t=21.
4) At t=21 rst_n is back at 1, so q_async stays 0 until the next edge.
5) At the edge at t=25 both flops load d=1 again: at t=26 both show 1.Answer: t=18 async=0 sync=1, t=21 async=0 sync=1, t=26 async=1 sync=1. The asynchronous flop obeys the pulse immediately and loses its state; the synchronous flop never notices a pulse that contains no clock edge.
Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus (4-state): the asynchronous flop clears during the pulse; the synchronous flop never sees it.
Assuming a reset pulse always resets everything it touches. A synchronous-reset flop (and any monitor sampled on the clock) is blind to a reset that rises and falls between edges, so a reset glitch can reset the asynchronous flops while the synchronous ones carry on, leaving the design in a mixed state.
Which style resets the design correctly if the clock is stopped while reset is asserted? Model answer: the asynchronous-assert style, because the flop clears without needing an edge; a purely synchronous reset needs a running clock for at least one edge while reset is asserted.