Difficulty: Medium · Puzzle 3 of 6 · Topic: Reset Puzzles
A reset synchroniser (two flops, D tied to 1, asynchronous clear) produces rst_out_n from an external rst_in_n. Clock edges are at 5, 15, 25, ... The input is asserted at t=1, released at t=12, asserted again at t=42 and released at t=47. List every time rst_out_n changes and its new value, and say why this circuit is built this way.
`timescale 1ns/1ns
module tb;
reg clk = 0;
reg rst_in_n = 1; // asynchronous reset request from outside
reg s1, s2; // s2 is the synchronised reset that the design uses
always #5 clk = ~clk; // posedges at 5, 15, 25, ...
always @(posedge clk or negedge rst_in_n)
if (!rst_in_n) begin s1 <= 1'b0; s2 <= 1'b0; end
else begin s1 <= 1'b1; s2 <= s1; end
always @(s2) $display("t=%0d rst_out_n=%b", $time, s2);
initial begin
#1 rst_in_n = 0;
#11 rst_in_n = 1; // released at t=12, between edges 5 and 15
#30 rst_in_n = 0; // asserted again at t=42
#5 rst_in_n = 1; // released again at t=47
#30 $finish;
end
endmoduleAssertion needs no clock; release needs two clock edges.
1) t=1: rst_in_n falls, both flops clear immediately, so s2 goes from X to 0 with no clock edge needed.
2) rst_in_n rises at t=12. The edge at t=15 loads s1=1; the edge at t=25 moves it to s2. rst_out_n rises at t=25.
3) rst_in_n falls at t=42: both flops clear asynchronously, rst_out_n falls at t=42, not at the next edge (45).
4) rst_in_n rises at t=47. Edge 55 sets s1, edge 65 sets s2: rst_out_n rises at t=65.
5) Why: asserting asynchronously puts the design in reset even when the clock is not running; releasing synchronously guarantees the release happens at a clock edge, so every flop sees it with recovery/removal margin and all leave reset on the same edge.Answer: rst_out_n changes at t=1 (to 0), t=25 (to 1), t=42 (to 0) and t=65 (to 1). Assertion is immediate; release is delayed to a clock edge two cycles after the input release.
Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus: the output falls with the input (asynchronous) and rises two clock edges after the input is released.
Saying the synchroniser delays reset assertion by two cycles. It does not: the clear is asynchronous, only the release is delayed. A bench that checks reset with clocked assertions will also see the assertion late and the release exactly two edges after the input rises.
What goes wrong if the synchroniser's flops use a synchronous clear instead of an asynchronous one? Model answer: assertion then waits for a clock edge, which never comes if the clock is stopped or gated off, and the flops downstream may never reset at all.