Difficulty: Easy · Puzzle 2 of 6 · Topic: Reset Puzzles
Two 4-bit counters run from the same clock. Only one has a reset. What do the printed lines show in a 4-state simulator, and why can the same bench pass in a 2-state simulator?
`timescale 1ns/1ns
module tb;
reg clk = 0, rst_n = 0;
reg [3:0] cnt_noreset, cnt_reset;
always #5 clk = ~clk; // posedges at 5, 15, 25, 35
always @(posedge clk) cnt_noreset <= cnt_noreset + 1;
always @(posedge clk)
if (!rst_n) cnt_reset <= 4'd0; else cnt_reset <= cnt_reset + 1;
initial begin
#6 $display("t=%0d noreset=%b reset=%b", $time, cnt_noreset, cnt_reset);
#6 rst_n = 1;
#4 $display("t=%0d noreset=%b reset=%b", $time, cnt_noreset, cnt_reset);
#10 $display("t=%0d noreset=%b reset=%b", $time, cnt_noreset, cnt_reset);
#10 $display("t=%0d noreset=%b reset=%b", $time, cnt_noreset, cnt_reset);
#10 $display("t=%0d noreset=%b reset=%b", $time, cnt_noreset, cnt_reset);
#1 $finish;
end
endmoduleWhat is X plus one?
1) Without a reset or an initial value a 4-state reg powers up as X. cnt_noreset <= cnt_noreset + 1 is X + 1 = X, so it stays xxxx for ever.
2) cnt_reset is held at 0 by the edge at t=5 (rst_n low), then rst_n rises at t=12.
3) The edge at t=15 is the first that sees rst_n=1, so it counts to 1; 25 gives 2; 35 gives 3.
4) In a 2-state simulator (or a tool that randomises or zeroes initial values) the unreset counter would start at a legal number and count, hiding the missing reset.Answer: t=6 noreset=xxxx reset=0000, t=16 noreset=xxxx reset=0001, t=26 noreset=xxxx reset=0010, t=36 noreset=xxxx reset=0011, t=46 noreset=xxxx reset=0100. The unreset counter is X for ever; a 2-state tool would show it counting normally.
Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus (4-state): the counter without a reset stays X; the one with a reset counts from the first edge that sees rst_n high.
Believing a flop 'starts at 0'. In silicon it powers up in a random state and in 4-state RTL it is X, and X survives increment, compare and shift. Seeing X in a 4-state sim is the cheap way to find a missing reset; a 2-state or randomised-init run can hide it.
Why is giving the register an initial value (reg [3:0] cnt = 0) not an acceptable fix for ASIC RTL? Model answer: initial values are not a reset mechanism in the ASIC flow (synthesis ignores or rejects them), so the silicon would still power up random; the register needs a real reset (or must be provably overwritten before use).