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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
    • Valid/Ready Handshake Puzzles
      • Counting Transfers in a Valid/Ready Trace
      • Which Cycle Drops VALID Illegally?
      • Payload Changes While Stalled
      • Both Sides Wait: The Handshake Deadlock
      • Registered READY Overflows a FIFO
      • Register Slice: 50% Throughput Without Data Errors
    • APB Protocol Puzzles
    • AXI Protocol Puzzles
    • FIFO, Arbitration and Credit Puzzles
    • Bus and Interface Protocol Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Valid/Ready Handshake Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Bus and Interface Protocol Puzzles
  4. Valid/Ready Handshake Puzzles
  5. Counting Transfers in a Valid/Ready Trace
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    VLSI DV Interview PuzzlesAll levels

    Counting Transfers in a Valid/Ready Trace

    A valid/ready interface (AXI-Stream style: both signals are sampled at every rising clock edge) shows the VALID and READY patterns below for 10 cycles. A beat moves only when both are high at the same edge. How many beats transfer, and in which cycles?

    Puzzle

    Difficulty: Easy · Puzzle 1 of 6 · Topic: Valid/Ready Handshake Puzzles

    A valid/ready interface (AXI-Stream style: both signals are sampled at every rising clock edge) shows the VALID and READY patterns below for 10 cycles. A beat moves only when both are high at the same edge. How many beats transfer, and in which cycles?

    Code

    tb.sv
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    `timescale 1ns/1ns
    module tb;
      localparam int N = 10;
      //                        cycle: 0123456789
      localparam bit [0:N-1] VALID = 10'b1110110111;
      localparam bit [0:N-1] READY = 10'b0110011101;
      bit clk = 0;
      int cyc = 0, xfers = 0;
      always #5 clk = ~clk;
      wire valid = VALID[cyc];
      wire ready = READY[cyc];
      always @(posedge clk) begin
        if (valid && ready) begin
          xfers++;
          $display("cycle %0d: transfer #%0d", cyc, xfers);
        end
        if (cyc == N-1) $display("total transfers = %0d", xfers);
        cyc <= cyc + 1;
      end
      initial #(10*N) $finish;
    endmodule

    Hint

    Mark the cycles where both bits are 1; ignore cycles where only one is high.

    Step-by-step solution

    Diagram
    1) VALID = 1110110111 and READY = 0110011101 (cycle 0 is the leftmost bit).
    2) AND the two: cycle 0 (1,0) no, 1 (1,1) yes, 2 (1,1) yes, 3 (0,0) no, 4 (1,0) no, 5 (1,1) yes, 6 (0,1) no, 7 (1,1) yes, 8 (1,0) no, 9 (1,1) yes.
    3) Five beats move: cycles 1, 2, 5, 7, 9.
    4) Cycles 0, 4 and 8 are stalls: the source offers a beat, the sink is not ready, and the same beat is offered again later.

    Answer

    Answer: 5 transfers, in cycles 1, 2, 5, 7 and 9. VALID is high in 8 cycles and READY in 6, but only the AND counts.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. The monitor counts valid && ready at each edge and reports five transfers in cycles 1, 2, 5, 7 and 9.

    Why candidates get it wrong

    Counting VALID-high cycles (8) turns three stalled cycles (0, 4, 8) into phantom beats. A stalled cycle is the SAME beat offered again, so a scoreboard that logs on VALID alone sees duplicates.

    Interviewer follow-up

    If a monitor wrongly logged a beat on every cycle with VALID high, how many duplicates would the scoreboard see here? Model answer: 3. VALID is high in 8 cycles but only 5 are transfers, so cycles 0, 4 and 8 (VALID high, READY low) would each be logged as an extra copy of the beat that completes later.

    Related topics

    • Back to Valid/Ready Handshake Puzzles

    • Bus and Interface Protocol Puzzles section

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    See also

    • Payload Changes While Stalled
    • Both Sides Wait: The Handshake Deadlock
    • Registered READY Overflows a FIFO