Difficulty: Easy · Puzzle 2 of 6 · Topic: Valid/Ready Handshake Puzzles
Rule under test (AXI4 / AXI4-Stream): once VALID is asserted it must stay asserted until the beat is accepted (VALID and READY both high at an edge). The trace below runs 7 cycles. Which cycle, if any, violates the rule, and what happens to the dropped beat?
`timescale 1ns/1ns
module tb;
localparam int N = 7;
// cycle: 0123456
localparam bit [0:N-1] VALID = 7'b1101010;
localparam bit [0:N-1] READY = 7'b0110011;
bit clk = 0;
int cyc = 0, bad = 0;
bit pv = 0, pr = 0; // previous-cycle valid / ready
always #5 clk = ~clk;
wire valid = VALID[cyc];
wire ready = READY[cyc];
always @(posedge clk) begin
if (pv && !pr && !valid) begin
bad++;
$display("VIOLATION cycle %0d: valid dropped while the previous beat was still waiting for ready", cyc);
end
if (valid && ready) $display("cycle %0d: transfer", cyc);
pv <= valid;
pr <= ready;
if (cyc == N-1) $display("violations = %0d", bad);
cyc <= cyc + 1;
end
initial #(10*N) $finish;
endmoduleVALID falling is only a problem if the previous cycle was a stall (VALID high, READY low).
1) VALID = 1101010, READY = 0110011.
2) Cycle 0: VALID=1, READY=0 -> stall. Cycle 1: VALID=1, READY=1 -> transfer.
3) Cycle 2: VALID falls. The previous cycle was a transfer, so this is legal.
4) Cycle 3: VALID=1, READY=0 -> stall. Cycle 4: VALID falls while the previous beat was never accepted -> violation.
5) Cycle 5: VALID=1, READY=1 transfers a beat, but it is a new offer; the beat that was stalled in cycle 3 was withdrawn and is lost. Cycle 6: VALID falls after a transfer, legal.Answer: Only cycle 4 violates the rule. The beat offered in cycle 3 was withdrawn without being accepted. Falling VALID in cycles 2 and 6 is legal because the previous cycle completed a transfer.
Checked by running the code in Verilator 5; the printed output supports the answer above. The checker looks at the previous cycle: only cycle 4 follows a stall, so it is the only violation.
Flagging every falling edge of VALID is wrong: VALID may drop right after a completed transfer. The check needs the PREVIOUS cycle (VALID high and READY low) as a condition, so a stateless 'VALID fell' rule gives false failures at cycles 2 and 6.
Is READY allowed to drop while VALID is low or high without a handshake? Model answer: Yes. The hold rule applies to the source (VALID and payload) only; a sink may deassert READY at any time, including after seeing VALID, which is why a source can never assume READY will still be high next cycle.