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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
    • Reset Puzzles
    • Clock Gating & Clock Mux Puzzles
    • CDC Basics Puzzles
      • MTBF Of Two Flops Versus Three
      • Back-to-Back Events Through a Toggle Synchroniser
      • Why Gray Code Across Clock Domains
      • A Four-Phase Handshake For a Bus
      • Full or Not in a Gray-Coded FIFO
      • Valid Crossed, Data Did Not
    • Verifying CDC & Reset Puzzles
    • Clock, Reset & CDC Puzzles: Tricky Q&A
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←CDC Basics Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Clock, Reset & CDC Puzzles
  4. CDC Basics Puzzles
  5. MTBF Of Two Flops Versus Three
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    VLSI DV Interview PuzzlesAll levels

    MTBF Of Two Flops Versus Three

    Use MTBF = exp(tr/tau) / (T0 * fclk * fdata) with tau = 100 ps, T0 = 50 ps, destination clock 500 MHz (T = 2 ns), average data rate fdata = 50 MHz, and flop setup time 150 ps. Take the resolution time of a synchroniser as the time the first flop has before the next flop's setup: one period for two flops, two periods for three flops, each minus 150 ps. Compute the MTBF for two flops and for three flops, and what doubling fdata does.

    Puzzle

    Difficulty: Medium · Puzzle 1 of 6 · Topic: CDC Basics Puzzles

    Use MTBF = exp(tr/tau) / (T0 * fclk * fdata) with tau = 100 ps, T0 = 50 ps, destination clock 500 MHz (T = 2 ns), average data rate fdata = 50 MHz, and flop setup time 150 ps. Take the resolution time of a synchroniser as the time the first flop has before the next flop's setup: one period for two flops, two periods for three flops, each minus 150 ps. Compute the MTBF for two flops and for three flops, and what doubling fdata does.

    Hint

    tr is 1.85 ns for two flops; exp(18.5) is about 1.08e8.

    Step-by-step solution

    Diagram
    1) Two flops: tr = 2 ns - 0.15 ns = 1.85 ns. exp(1.85 ns / 100 ps) = exp(18.5) = 1.08e8.
    2) Denominator: T0 * fclk * fdata = 50e-12 * 500e6 * 50e6 = 1.25e6 per second.
    3) MTBF(two flops) = 1.08e8 / 1.25e6 = 86.6 s, about a minute and a half.
    4) Three flops: tr = 4 ns - 0.15 ns = 3.85 ns; exp(38.5) = 5.25e16; MTBF = 5.25e16 / 1.25e6 = 4.2e10 s, about 1,330 years.
    5) Doubling fdata doubles the denominator, so the MTBF halves (86.6 s to 43.3 s): the dependence on data rate is linear, on resolution time it is exponential.

    Answer

    Answer: Two flops: about 87 s (far too low for a product). Three flops: about 4.2e10 s, roughly 1,330 years. Doubling the data rate halves the MTBF. The model is an assumed formula: real tau, T0 and tr come from the library and the clock tree.

    How this was checked

    Checked by running a model of the rule in a Python model. A computational check of the stated formula. Metastability is not simulated; only its published model is evaluated.

    Why candidates get it wrong

    Saying 'two flops are always enough'. With a fast clock the resolution time left after setup is short and the exponent small: at 500 MHz the two-flop figure is under two minutes in this example. The standard requirement (e.g. a 1,000-year MTBF) decides the number of stages, and dropping the clock rate or adding a stage is exponential, not linear.

    Interviewer follow-up

    What does a gate-level or RTL simulation tell you about this number? Model answer: nothing: zero-delay RTL has no metastability and gate-level sims only show the logic value, so MTBF comes from the formula and library characterisation (tau and T0), not from simulation.

    Related topics

    • Back to CDC Basics Puzzles

    • Clock, Reset & CDC Puzzles section

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    See also

    • Why Gray Code Across Clock Domains
    • A Four-Phase Handshake For a Bus
    • Full or Not in a Gray-Coded FIFO