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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
    • Reset Puzzles
    • Clock Gating & Clock Mux Puzzles
    • CDC Basics Puzzles
      • MTBF Of Two Flops Versus Three
      • Back-to-Back Events Through a Toggle Synchroniser
      • Why Gray Code Across Clock Domains
      • A Four-Phase Handshake For a Bus
      • Full or Not in a Gray-Coded FIFO
      • Valid Crossed, Data Did Not
    • Verifying CDC & Reset Puzzles
    • Clock, Reset & CDC Puzzles: Tricky Q&A
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←CDC Basics Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Clock, Reset & CDC Puzzles
  4. CDC Basics Puzzles
  5. Back-to-Back Events Through a Toggle Synchroniser
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    VLSI DV Interview PuzzlesAll levels

    Back-to-Back Events Through a Toggle Synchroniser

    A toggle synchroniser (source toggles a flop on every event; the destination double-flops it and XORs the last two stages to produce one event per toggle) crosses from a 10 ns clock to a 24 ns clock. Pair A: events at source edges 25 and 35. Pair B: events at source edges 85 and 115. The destination edges are at 12, 36, 60, 84, 108, ... How many destination events are counted for each pair? Assume the destination samples the toggle level exactly at its edges (no metastability).

    Puzzle

    Difficulty: Medium · Puzzle 2 of 6 · Topic: CDC Basics Puzzles

    A toggle synchroniser (source toggles a flop on every event; the destination double-flops it and XORs the last two stages to produce one event per toggle) crosses from a 10 ns clock to a 24 ns clock. Pair A: events at source edges 25 and 35. Pair B: events at source edges 85 and 115. The destination edges are at 12, 36, 60, 84, 108, ... How many destination events are counted for each pair? Assume the destination samples the toggle level exactly at its edges (no metastability).

    Code

    tb.sv
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    `timescale 1ns/1ns
    module tb;
      reg clks = 0, clkd = 0;
      always #5  clks = ~clks;                    // source period 10: posedges at 5, 15, 25, ...
      always #12 clkd = ~clkd;                    // destination period 24: posedges at 12, 36, 60, 84, 108, ...
      reg pulse = 0;                              // an event is requested at every source edge where pulse=1
      reg tog = 0;
      always @(posedge clks) if (pulse) tog <= ~tog;
      reg f1 = 0, f2 = 0, f3 = 0;
      always @(posedge clkd) begin f1 <= tog; f2 <= f1; f3 <= f2; end
      wire ev = f2 ^ f3;                          // one destination event per toggle seen
      integer events = 0;
      always @(posedge clkd) if (ev) events <= events + 1;
      initial begin
        #20  pulse = 1;                           // events at source edges 25 and 35 (consecutive cycles)
        #20  pulse = 0;
        #38  $display("t=%0d after pair A (edges 25 and 35): events=%0d", $time, events);
        #2   pulse = 1;                           // t=80: event at source edge 85
        #10  pulse = 0;
        #20  pulse = 1;                           // t=110: event at source edge 115 (30 ns later)
        #10  pulse = 0;
        #120 $display("t=%0d after pair B (edges 85 and 115): events=%0d", $time, events);
        #1   $finish;
      end
    endmodule

    Hint

    How long is the toggle level stable between the two toggles of each pair?

    Step-by-step solution

    Diagram
    1) Pair A: the toggle flips after the edge at 25 (to 1) and again after the edge at 35 (back to 0): the level is high for only 10 ns, between 25 and 35.
    2) Destination edges at 12 and 36 fall outside that window, so the destination never sees the level high and counts 0 events: both are lost.
    3) Pair B: the toggle is high from 85 to 115, a window of 30 ns, which contains the destination edge at 108.
    4) The destination sees 1 at 108 and 0 at 132, so it detects two changes and counts 2 events.
    5) Rule: successive events must be spaced by more than one destination period (plus margin) so that every toggle level lasts for at least one destination edge.

    Answer

    Answer: Pair A (10 ns apart): 0 events counted, both are lost. Pair B (30 ns apart): both counted, 2 events. A toggle synchroniser needs successive events separated by more than one destination clock period (here 24 ns); closer events can cancel and vanish.

    How this was checked

    Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus: the events 10 ns apart cancel in the toggle and are lost; events 30 ns apart are both counted. The check samples the level exactly at the edge (no metastability).

    Why candidates get it wrong

    Believing a toggle synchroniser makes the crossing lossless. It removes the pulse-width problem, but the toggle must stay unchanged for at least one destination edge, so there is a minimum spacing between events; if events can be closer than that the design needs a handshake or a FIFO.

    Interviewer follow-up

    Does a destination period of 24 ns guarantee pair B in every phase? Model answer: yes under the stated spacing rule: any window of 30 ns, longer than one 24 ns period, contains at least one destination edge, whatever the phase; a spacing of 24 ns or less would depend on phase and would not be safe.

    Related topics

    • Back to CDC Basics Puzzles

    • Clock, Reset & CDC Puzzles section

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    See also

    • A Four-Phase Handshake For a Bus
    • Full or Not in a Gray-Coded FIFO
    • Valid Crossed, Data Did Not