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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
    • Reset Puzzles
    • Clock Gating & Clock Mux Puzzles
    • CDC Basics Puzzles
    • Verifying CDC & Reset Puzzles
      • RTL Simulation Cannot Tell One Flop From Two
      • Clock Ratios That Hide Phase Bugs
      • A Reset Checker That Never Fires
      • Three Muxes, One Unknown Select
      • Gate-Level Skew Shoots Data Through
      • Reset Ordering Assertion: Same Edge or Strictly Later?
    • Clock, Reset & CDC Puzzles: Tricky Q&A
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Verifying CDC & Reset Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Clock, Reset & CDC Puzzles
  4. Verifying CDC & Reset Puzzles
  5. Clock Ratios That Hide Phase Bugs
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    VLSI DV Interview PuzzlesAll levels

    Clock Ratios That Hide Phase Bugs

    A testbench drives a 10 ns source clock and a destination clock, both starting at t=0. How many different positions of the destination edge relative to the source period does the bench exercise (edges taken over 1,000 ns) for destination periods of 20 ns, 13 ns and 15 ns? What do you change to cover more?

    Puzzle

    Difficulty: Medium · Puzzle 2 of 6 · Topic: Verifying CDC & Reset Puzzles

    A testbench drives a 10 ns source clock and a destination clock, both starting at t=0. How many different positions of the destination edge relative to the source period does the bench exercise (edges taken over 1,000 ns) for destination periods of 20 ns, 13 ns and 15 ns? What do you change to cover more?

    Hint

    Look at the destination edge times modulo 10.

    Step-by-step solution

    Diagram
    1) 20 ns: edges at 0, 20, 40, ...; modulo 10 every edge falls at 0. One phase only: the destination edge is always exactly aligned with a source edge.
    2) 13 ns: edges at 0, 13, 26, 39, 52, ...; modulo 10 gives 0, 3, 6, 9, 2, 5, 8, 1, 4, 7: all ten phases.
    3) 15 ns: edges at 0, 15, 30, ...; modulo 10 gives 0, 5, 0, 5: two phases.
    4) A bench with a 2:1 ratio and aligned starts exercises one fixed alignment for the entire run, so a bug that appears only at some other phase is never hit.
    5) Fixes: random start offset and random ratio or period per test, jitter on the clock edges, and a sweep that is long enough to cover the phases; each run still covers a limited set of phases, so repeat across seeds.

    Answer

    Answer: 20 ns: 1 phase; 13 ns: 10 phases; 15 ns: 2 phases. Randomise the start offset and the period (or add jitter) per seed and run many seeds; an integer-ratio aligned clock pair never exercises most phases.

    How this was checked

    Checked by running a model of the rule in a Python model. A Python model counts distinct edge positions of the destination clock modulo the source period.

    Why candidates get it wrong

    Using a neat 2:1 or 1:1 clock ratio because it is 'easier to debug'. The relation between the clocks is part of the stimulus: a fixed alignment is a single test point, and the bugs live in the phases you did not run.

    Interviewer follow-up

    If you add random jitter to the 20 ns clock, does one run now cover all ten phases? Model answer: only if the jitter spans the 10 ns range or is accumulated over time; small jitter covers a small neighbourhood of one phase, so use a randomised start offset and ratio per run in addition.

    Related topics

    • Back to Verifying CDC & Reset Puzzles

    • Clock, Reset & CDC Puzzles section

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    See also

    • Three Muxes, One Unknown Select
    • Gate-Level Skew Shoots Data Through
    • Reset Ordering Assertion: Same Edge or Strictly Later?