Day 1

UVM Testbench Puzzles: Factory and config_db; UVM Testbench Puzzles: Sequences and Sequencers

uvm-config-01: Virtual Interface Set with a Relative Path from Top (E); uvm-config-02: Child Set Later, Parent Set Wins (M); uvm-config-03: Config Object Set as Base, Got as Derived (H); uvm-config-04: Config Set Too Late for build_phase (E); uvm-config-05: Factory Instance Override Path: Relative or Full (M); uvm-config-06: Override of a Parameterized Component (H); uvm-seq-01: try_next_item Loop That Never Lets Time Pass (E); uvm-seq-02: When finish_item Returns (M); uvm-seq-03: lock Versus grab Ordering (M); uvm-seq-04: Inline Constraint That Constrains Nothing (M); uvm-seq-05: Virtual Sequence Started With null (E); uvm-seq-06: Default Sequence Ends at Time Zero (H)

Day 2

UVM Testbench Puzzles: Analysis, Scoreboards and RAL; Clock, Reset & CDC Puzzles: Reset Puzzles; Clock, Reset & CDC Puzzles: Clock Gating & Clock Mux Puzzles

uvm-sb-01: Waiting Inside write() (E); uvm-sb-02: Two Analysis Imps, One write() (M); uvm-sb-03: Auto-Predict, No Predictor, and a Second Master (H); uvm-sb-04: Desired, Mirrored and update() (E); uvm-sb-05: Backdoor Read of a Clear-on-Read Register (M); uvm-sb-06: Register Reads Return Zero With a Good Waveform (H); crc-rst-01: A Reset Pulse Between Two Clock Edges (E); crc-rst-02: The Counter Nobody Reset (E); crc-rst-03: Asynchronous Assert, Synchronous Release (M); crc-rst-04: Reset Has Lower Priority Than Enable (E); crc-rst-05: Reset Release Order Across Domains (M); crc-rst-06: Reset Released With a Blocking Assignment (H); crc-clk-01: AND Gate Fed Straight From a Flop (M); crc-clk-02: A Latch Makes the Gate Safe (E); crc-clk-03: Which Gate Wants Which Phase? (M); crc-clk-04: Switching a Clock Mux With the Select (M); crc-clk-05: The Glitch-Free Clock Switch (H); crc-clk-06: Does the Gated Flop See the Old Data? (M)

Day 3

Clock, Reset & CDC Puzzles: CDC Basics Puzzles; Clock, Reset & CDC Puzzles: Verifying CDC & Reset Puzzles; Bus and Interface Protocol Puzzles: Valid/Ready Handshake Puzzles

crc-cdc-01: MTBF Of Two Flops Versus Three (M); crc-cdc-02: Back-to-Back Events Through a Toggle Synchroniser (M); crc-cdc-03: Why Gray Code Across Clock Domains (E); crc-cdc-04: A Four-Phase Handshake For a Bus (H); crc-cdc-05: Full or Not in a Gray-Coded FIFO (H); crc-cdc-06: Valid Crossed, Data Did Not (E); crc-ver-01: RTL Simulation Cannot Tell One Flop From Two (E); crc-ver-02: Clock Ratios That Hide Phase Bugs (M); crc-ver-03: A Reset Checker That Never Fires (M); crc-ver-04: Three Muxes, One Unknown Select (E); crc-ver-05: Gate-Level Skew Shoots Data Through (H); crc-ver-06: Reset Ordering Assertion: Same Edge or Strictly Later? (H); proto-hs-01: Counting Transfers in a Valid/Ready Trace (E); proto-hs-02: Which Cycle Drops VALID Illegally? (E); proto-hs-03: Payload Changes While Stalled (E); proto-hs-04: Both Sides Wait: The Handshake Deadlock (M); proto-hs-05: Registered READY Overflows a FIFO (H); proto-hs-06: Register Slice: 50% Throughput Without Data Errors (H)

Day 4

Bus and Interface Protocol Puzzles: APB Protocol Puzzles; Bus and Interface Protocol Puzzles: AXI Protocol Puzzles; Bus and Interface Protocol Puzzles: FIFO, Arbitration and Credit Puzzles

proto-apb-01: Setup, Access and Completed Transfers (E); proto-apb-02: Two Wait States: Total Cycles and Write Moment (E); proto-apb-03: When Is PSLVERR Real? (M); proto-apb-04: Can Two Transfers Fit in Three Cycles? (M); proto-apb-05: Write Data Changes in a Wait State (M); proto-apb-06: Sampling PRDATA One Cycle Too Early (H); proto-axi-01: The 4 KB Rule Splits a Burst (E); proto-axi-02: OKAY, SLVERR or DECERR? (M); proto-axi-03: WRAP Burst Address Sequence (M); proto-axi-04: WLAST One Beat Early (M); proto-axi-05: How Many Read Orders Are Legal? (M); proto-axi-06: Whose Data Is This? W Has No ID (H); proto-fifo-01: Sizing a FIFO for a Rate Mismatch Burst (E); proto-fifo-02: Empty and Full With Simultaneous Read and Write (E); proto-fifo-03: Full and Empty From Gray-Coded Pointers (H); proto-fifo-04: Round-Robin Grants and the Starved Requester (M); proto-fifo-05: Credit Window vs Round-Trip Time (M); proto-fifo-06: Circular Wait Between Two Full Queues (H)

Day 5 (review)

Cheatsheet; Coverage Not Closing; Race That Only Shows on Silicon-Like Gate-Level Timing; Coverage Closed at 100 Percent but a Bug Escaped; Full mock round: three random puzzles per section, timed, scored, out loud.

Re-do misses