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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
    • ACE Coherent Transactions
    • Snoop & Cache Maintenance
    • CHI Topology Basics
      • CHI Topology Basics: Mechanism
      • CHI Topology Basics: Inputs & Outputs
      • CHI Topology Basics: Reports & Metrics
      • CHI Topology Basics: Debug Playbook
      • CHI Topology Basics: Worked Example
      • CHI Topology Basics: Pitfalls & Red Flags
      • CHI Topology Basics: Interview Drills
      • CHI Topology Basics: Review Checklist
      • CHI Topology Basics: Theory Deep Dive
      • CHI Topology Basics: Design Space
      • CHI Topology Basics: Expanded Case Study
      • CHI Topology Basics: Step-by-Step Walkthrough
      • CHI Topology Basics: Comparison Matrix
      • CHI Topology Basics: Software / Programmer View
      • CHI Topology Basics: Silicon PPA Impact
    • Coherence Fabric Debug
    • Coherence Fabrics (ACE / CHI): Tricky Q&A
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹CHI Topology Basics
  1. Topics
  2. Bus Protocols
  3. Coherence Fabrics (ACE / CHI)
  4. CHI Topology Basics
  5. CHI Topology Basics: Reports & Metrics

Interface Protocols · All levels

CHI Topology Basics: Reports & Metrics

Reports & Metrics for CHI Topology Basics.

On this page

    Reports and metrics

    Reports & Metrics for CHI Topology Basics focuses on request retry rate, directory occupancy, p99 fabric latency. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    The job of a report is to turn request retry rate, directory occupancy, p99 fabric latency into a decision. A single average number is almost never enough; you need the distribution, the traffic class breakdown, and a clear gap between legal maximum and product target.

    Metric movement

    Diagram
    METRIC GRAPH — request retry rate, directory occupancy, p99 fabric latency
    
    throughput / success
      ^
      |                         target
      |                       - - - - - - -
      |                  o after bounded fix
      |              o
      |         o baseline
      |    o failing run
      +--------------------------------------> experiment
        config A     isolated root cause     accepted change
    
    Readout:
      - compare identical payload, clock, reset, traffic seed, and firmware setup
      - separate headline bandwidth from useful payload bandwidth
      - explain why the protocol mechanism moved the metric

    Latency distribution

    Diagram
    LATENCY HISTOGRAM — CHI Topology Basics
    
    count
      |               ███
      |             ███████
      |          █████████████
      |        █████████████████        <- long tail = the real complaint
      |      ████████████████████████████
      +------------------------------------> latency
       p50      p90    p95       p99  (watch p99, not the average)
    
    Average hides the tail; product pain lives at p95/p99.
    • Track request retry rate, directory occupancy, p99 fabric latency by traffic class, payload size, and clock/reset mode.

    • Report p50/p95/p99 latency when user-visible stalls matter.

    • Include legal maximums and product targets; they are not the same thing.

    • Always store the metric next to the artifact that produced it.

    Protocol deep dive

    Coherence extends memory transactions with snoop and state — traffic multiplies when software shares cache lines.

    Concept diagram

    Diagram
    COHERENCE TRAFFIC FLOW
    
    RN issues coherent read
       -> HN looks up directory
       -> snoops to sharers
       -> data + state update returned
    
    False sharing: different variables, same cache line -> coherence storm.

    Metric graph

    Diagram
    COHERENCY TRAFFIC STACK
    
    data fetch        ████████
    snoop responses   ██████████████
    writebacks        ██████
    maintenance ops   ████
    
    High snoop stack with good IPC -> suspect line sharing before faster NoC.

    Metrics and artifacts to collect

    • snoop rate

    • intervention latency

    • coherency transaction mix

    • false sharing indicators

    Mini case study

    Benchmark IPC looked fine but system power spiked: per-core counters were on one cache line. Padding counters fixed coherency traffic without any NoC change.

    Debug branches

    • If snoop latency high, check home node placement and directory policy.

    • If ordering bug, run litmus sequences before microarch changes.

    • If traffic storm, profile cache line sharing in software layout.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    How to read the numbers

    request retry rate, directory occupancy, p99 fabric latency must be split by traffic class, payload size, and reset mode.

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    See also

    • CHI Topology Basics: Mechanism
    • CHI Topology Basics: Worked Example
    • CHI Topology Basics: Pitfalls & Red Flags