Silicon, power, area, and timing impact

Snoop filters, directories, and reorder buffers add area, power, and validation depth.

Area drivers

• FIFOs and reorder buffers scale with outstanding depth

• Wide muxes at bridges and fabric ports

• Scoreboards and ID trackers for verification-visible RTL

• PHY/SerDes macros for high-speed attachments

Power drivers

• Toggling wide buses during idle DMA

• PHY link states (L0 vs low-power)

• Clock gating vs wake-up latency tradeoff

Timing and frequency impact

• Channel handshake loops (valid/ready, credit return)

• Cross-clock domain paths at fabric boundaries

• PHY training margin vs frequency target

PD and floorplan consequences

• Place memory controller near DRAM PHY

• Keep coherent home nodes near CPU clusters

• Route high-speed lanes with SI-aware floorplan

Verification burden

• Legal transaction combinations grow with modes

• Ordering and coherence require directed + random stress

• Compliance mapping must trace to requirements

PPA SNAPSHOT — CHI Topology Basics

area     ████████░░  FIFOs + bridges
power    ██████░░░░  link/PHY dependent
timing   ███████░░░  handshake paths
verif    █████████░  modes × ordering

Signoff requires workload proof, not block-level optimism.

PPA takeaways

• Protocol features are gates and wires, not abstractions

• Every added mode needs a regression owner

• PD placement changes latency as much as microarchitecture

Design option PPA snapshot

BEFORE / AFTER — CHI Topology Basics

           failing        target
metric  |    ●              ┄┄┄┄┄┄┄
        |     \
        |      \___ ● bounded fix
        |           \
        |            ● validated
        +-------------------------------> change set
Prove the mechanism moved the metric; one good dot is not proof.

Protocol deep dive

Coherence extends memory transactions with snoop and state — traffic multiplies when software shares cache lines.

Concept diagram

COHERENCE TRAFFIC FLOW

RN issues coherent read
   -> HN looks up directory
   -> snoops to sharers
   -> data + state update returned

False sharing: different variables, same cache line -> coherence storm.

Metric graph

COHERENCY TRAFFIC STACK

data fetch        ████████
snoop responses   ██████████████
writebacks        ██████
maintenance ops   ████

High snoop stack with good IPC -> suspect line sharing before faster NoC.

Metrics and artifacts to collect

• snoop rate

• intervention latency

• coherency transaction mix

• false sharing indicators

Mini case study

Benchmark IPC looked fine but system power spiked: per-core counters were on one cache line. Padding counters fixed coherency traffic without any NoC change.

Debug branches

• If snoop latency high, check home node placement and directory policy.

• If ordering bug, run litmus sequences before microarch changes.

• If traffic storm, profile cache line sharing in software layout.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read CHI Topology Basics against one concrete product workload, not a synthetic directed test.

CHI separates request, response, data, and snoop flows across nodes with directory and home-node responsibilities.