CHI Topology Basics: Step-by-Step Walkthrough

Step-by-step analysis walkthrough

Follow this when you own CHI Topology Basics in a protocol review or bring-up war room.

1. State expected transaction in plain language (who initiates, what completes).

2. Draw layer stack and mark clock/reset boundaries.

3. List channels: request, data, response, snoop, credit, or lane.

4. Tag ID/address/endpoint on the failing run.

5. Find first cycle where progress stops or semantics change.

6. Check bridge: width, ID remap, burst, ordering attributes.

7. Check flow control: ready, credit, FIFO, link state.

8. Check firmware/register mode vs hardware capability.

9. Build minimal replay; confirm legal vs illegal per spec.

10. Estimate metric delta from proposed fix.

11. Run compliance + product traffic regression matrix.

12. Write signoff memo with owners and artifacts attached.

Artifacts to collect

• CHI node map, VC utilization report, request/response correlation log

• VIP transaction log

• Waveform with annotations

• Spec clause reference

• Regression manifest

Decision memo template

PROTOCOL DECISION MEMO — CHI Topology Basics
metric:
transaction id:
layer:
hypothesis:
experiment:
fix:
validation:
owners: fabric architect, NoC owner, performance owner

Reference visuals

CHI node types on a mesh

CHI MESH (RN = request node, HN = home node, SN = slave node)

   RN-F --- X --- X --- RN-I
    |       |     |       |
    X --- HN-F --- X --- X
    |       |     |       |
   SN  --- X --- HN-F --- SN

RN: cores/accelerators that issue requests
HN: home node owns coherency + directory for an address range
SN: memory/peripheral endpoints

Latency = hops x per-hop cost; placement matters.

Protocol deep dive

Coherence extends memory transactions with snoop and state — traffic multiplies when software shares cache lines.

Concept diagram

COHERENCE TRAFFIC FLOW

RN issues coherent read
   -> HN looks up directory
   -> snoops to sharers
   -> data + state update returned

False sharing: different variables, same cache line -> coherence storm.

Metric graph

COHERENCY TRAFFIC STACK

data fetch        ████████
snoop responses   ██████████████
writebacks        ██████
maintenance ops   ████

High snoop stack with good IPC -> suspect line sharing before faster NoC.

Metrics and artifacts to collect

• snoop rate

• intervention latency

• coherency transaction mix

• false sharing indicators

Mini case study

Benchmark IPC looked fine but system power spiked: per-core counters were on one cache line. Padding counters fixed coherency traffic without any NoC change.

Debug branches

• If snoop latency high, check home node placement and directory policy.

• If ordering bug, run litmus sequences before microarch changes.

• If traffic storm, profile cache line sharing in software layout.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read CHI Topology Basics against one concrete product workload, not a synthetic directed test.

CHI separates request, response, data, and snoop flows across nodes with directory and home-node responsibilities.