Scoreboard & Checker Strategy: Design Space

Design space exploration

For Scoreboard & Checker Strategy, senior architects map options against false fail rate, escaped bug count, response match latency on the product workload — not on a single directed test.

Option A — conservative

• Minimal / simple: helps timing, area, verification

• Risk: bandwidth and latency tails

• Validate with: control paths and low-rate peripherals

Option B — buffered / outstanding

• Buffered / outstanding: helps throughput under latency

• Risk: deadlock and debug complexity

• Validate with: DMA and memory-class traffic

Option C — QoS / arbitration

• QoS / arbitration: helps product-critical traffic wins

• Risk: verification state explosion

• Validate with: mixed CPU/GPU/DMA SoCs

Option D — software-first

• Software contract: helps predictable programming model

• Risk: portability and driver cost

• Validate with: platforms with long SW lifetime

DESIGN SPACE — Scoreboard & Checker Strategy

        performance
            ^
            |     [C] QoS-heavy
            |        *
            |   [B] buffered *
            |              *
            | [A] simple *
            +--------------------> complexity
                      [D] SW-first

Pick the smallest option that moves false fail rate, escaped bug count, response match latency on the product workload.

Design pitfalls

• Sizing for peak headline bandwidth instead of payload efficiency

• Adding outstanding depth without ordering analysis

• Choosing aggressive hardware before a reduced sequence proves the mechanism

Tradeoff curve

BEFORE / AFTER — Scoreboard & Checker Strategy

           failing        target
metric  |    ●              ┄┄┄┄┄┄┄
        |     \
        |      \___ ● bounded fix
        |           \
        |            ● validated
        +-------------------------------> change set
Prove the mechanism moved the metric; one good dot is not proof.

Protocol deep dive

Verification closes the gap between 'works in directed test' and 'legal under all stressed traffic'.

Concept diagram

VERIFICATION CLOSURE LOOP

spec clause -> test -> assertion -> coverage -> waiver -> signoff
                  ^                           |
                  +--------- gap found --------+

Metric graph

COVERAGE vs ESCAPE RATE

escapes
  |*
  | *
  |  *
  |   **  <- knee: more random helps
  |     ****
  +----------------> constrained-random depth

Metrics and artifacts to collect

• compliance pass rate

• coverage closure

• scoreboard mismatch rate

• assertion fire count

• waiver log

Mini case study

Block passed VIP compliance but chip failed: system test omitted cross-master ID reuse through a bridge. Scoreboard key did not include upstream port ID.

Debug branches

• If VIP pass but silicon fail, check integration assumptions.

• If scoreboard noisy, fix key (ID+port+addr).

• If coverage plateau, add compliance gap analysis not more repeats.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read Scoreboard & Checker Strategy against one concrete product workload, not a synthetic directed test.

scoreboards correlate requests and responses while assertions check local temporal rules and illegal combinations.