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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
    • VIP & Agent Architecture
    • Scoreboard & Checker Strategy
      • Scoreboard & Checker Strategy: Mechanism
      • Scoreboard & Checker Strategy: Inputs & Outputs
      • Scoreboard & Checker Strategy: Reports & Metrics
      • Scoreboard & Checker Strategy: Debug Playbook
      • Scoreboard & Checker Strategy: Worked Example
      • Scoreboard & Checker Strategy: Pitfalls & Red Flags
      • Scoreboard & Checker Strategy: Interview Drills
      • Scoreboard & Checker Strategy: Review Checklist
      • Scoreboard & Checker Strategy: Theory Deep Dive
      • Scoreboard & Checker Strategy: Design Space
      • Scoreboard & Checker Strategy: Expanded Case Study
      • Scoreboard & Checker Strategy: Step-by-Step Walkthrough
      • Scoreboard & Checker Strategy: Comparison Matrix
      • Scoreboard & Checker Strategy: Software / Programmer View
      • Scoreboard & Checker Strategy: Silicon PPA Impact
    • Compliance & Coverage Plan
    • Protocol Waveform Debug
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Scoreboard & Checker Strategy
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. Scoreboard & Checker Strategy
  5. Scoreboard & Checker Strategy: Mechanism

Interface Protocols · All levels

Scoreboard & Checker Strategy: Mechanism

Mechanism for Scoreboard & Checker Strategy.

On this page

    Mechanism to understand

    Mechanism for Scoreboard & Checker Strategy focuses on false fail rate, escaped bug count, response match latency. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    scoreboards correlate requests and responses while assertions check local temporal rules and illegal combinations. Think of it as a contract enforced at boundaries: the sender promises stability and legality, the receiver promises forward progress, and the fabric in between promises not to silently change identity or ordering.

    • Identify the transaction boundary: request, data, response, completion, or retry.

    • Identify the flow-control boundary: valid/ready, grant, credit, FIFO depth, or lane state.

    • Identify what the receiver is allowed to assume and what the sender must hold stable.

    Layered view

    Diagram
    PROTOCOL STACK VIEW — Scoreboard & Checker Strategy
    
    software / firmware intent
            |
            v
    transaction semantics: address, ID, length, attributes, ordering
            |
            v
    link / channel behavior: handshake, credits, backpressure, retries
            |
            v
    physical or timing layer: clocking, reset, pins, lanes, PHY
            |
            v
    observability: waveform, VIP transaction, counter, analyzer trace
    
    Debug rule: never jump layers without carrying the transaction identity with you.

    Scoreboard correlation

    Diagram
    SCOREBOARD = MATCH REQUEST TO RESPONSE
    
    inbound req  : key = {id, addr}
    outbound resp: key = {id}
            |
            v
      map[key] = expected ; on response compare actual
            |
       mismatch -> log first failing key + timestamp (not the 100th)
    
    Assertions catch LOCAL rules; scoreboards catch END-TO-END correctness.

    Layer responsibilities

    Diagram
    LAYER RESPONSIBILITY — Scoreboard & Checker Strategy
    
    layer          owns                         common failure
    -----------    --------------------------   -----------------------
    software       intent, ordering needs       wrong assumption
    transaction    id/addr/len/attributes       ordering / outstanding
    link/channel   handshake, credits, retry    backpressure / deadlock
    physical       clock/reset/lanes/PHY        timing / training / SI
    observability  waveform/log/counter         missing evidence

    Protocol deep dive

    Verification closes the gap between 'works in directed test' and 'legal under all stressed traffic'.

    Concept diagram

    Diagram
    VERIFICATION CLOSURE LOOP
    
    spec clause -> test -> assertion -> coverage -> waiver -> signoff
                      ^                           |
                      +--------- gap found --------+

    Metric graph

    Diagram
    COVERAGE vs ESCAPE RATE
    
    escapes
      |*
      | *
      |  *
      |   **  <- knee: more random helps
      |     ****
      +----------------> constrained-random depth

    Metrics and artifacts to collect

    • compliance pass rate

    • coverage closure

    • scoreboard mismatch rate

    • assertion fire count

    • waiver log

    Mini case study

    Block passed VIP compliance but chip failed: system test omitted cross-master ID reuse through a bridge. Scoreboard key did not include upstream port ID.

    Debug branches

    • If VIP pass but silicon fail, check integration assumptions.

    • If scoreboard noisy, fix key (ID+port+addr).

    • If coverage plateau, add compliance gap analysis not more repeats.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    Mechanism deep dive

    scoreboards correlate requests and responses while assertions check local temporal rules and illegal combinations.

    Walk the transaction forward: request accepted → data moves → response completes → software visible effect.

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    See also

    • Scoreboard & Checker Strategy: Reports & Metrics
    • Scoreboard & Checker Strategy: Debug Playbook
    • Scoreboard & Checker Strategy: Worked Example