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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
    • VIP & Agent Architecture
    • Scoreboard & Checker Strategy
      • Scoreboard & Checker Strategy: Mechanism
      • Scoreboard & Checker Strategy: Inputs & Outputs
      • Scoreboard & Checker Strategy: Reports & Metrics
      • Scoreboard & Checker Strategy: Debug Playbook
      • Scoreboard & Checker Strategy: Worked Example
      • Scoreboard & Checker Strategy: Pitfalls & Red Flags
      • Scoreboard & Checker Strategy: Interview Drills
      • Scoreboard & Checker Strategy: Review Checklist
      • Scoreboard & Checker Strategy: Theory Deep Dive
      • Scoreboard & Checker Strategy: Design Space
      • Scoreboard & Checker Strategy: Expanded Case Study
      • Scoreboard & Checker Strategy: Step-by-Step Walkthrough
      • Scoreboard & Checker Strategy: Comparison Matrix
      • Scoreboard & Checker Strategy: Software / Programmer View
      • Scoreboard & Checker Strategy: Silicon PPA Impact
    • Compliance & Coverage Plan
    • Protocol Waveform Debug
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Scoreboard & Checker Strategy
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. Scoreboard & Checker Strategy
  5. Scoreboard & Checker Strategy: Worked Example

Interface Protocols · All levels

Scoreboard & Checker Strategy: Worked Example

Worked Example for Scoreboard & Checker Strategy.

On this page

    Worked example

    Worked Example for Scoreboard & Checker Strategy focuses on false fail rate, escaped bug count, response match latency. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    A product workload shows false fail rate, escaped bug count, response match latency. The first review mistake is to blame the whole interface. A better review starts by pinning one transaction, proving where protocol progress stopped, and checking whether the observed behavior is legal for Scoreboard & Checker Strategy.

    Sequence under inspection

    Diagram
    SEQUENCE — Scoreboard & Checker Strategy
    
      initiator            interconnect/PHY            target
          |  request (id) ------->  |                     |
          |                         |  forward ----------> |
          |                         |                     | work
          |                         |  <---- response ---- |
          |  <----- complete ------ |                     |
          |
       metric captured here: false fail rate, escaped bug count, response match latency

    Scoreboard correlation

    Diagram
    SCOREBOARD = MATCH REQUEST TO RESPONSE
    
    inbound req  : key = {id, addr}
    outbound resp: key = {id}
            |
            v
      map[key] = expected ; on response compare actual
            |
       mismatch -> log first failing key + timestamp (not the 100th)
    
    Assertions catch LOCAL rules; scoreboards catch END-TO-END correctness.
    1. Capture the failing waveform and transaction log.

    2. Tag the request ID, address, endpoint, or lane.

    3. Find the first response, retry, stall, or missing completion.

    4. Compare against scoreboard key map, assertion failure waveform, expected/actual transaction diff.

    5. Choose one reversible fix and write the regression list before editing RTL or firmware.

    Did the fix work?

    Diagram
    BEFORE / AFTER — Scoreboard & Checker Strategy
    
               failing        target
    metric  |    ●              ┄┄┄┄┄┄┄
            |     \
            |      \___ ● bounded fix
            |           \
            |            ● validated
            +-------------------------------> change set
    Prove the mechanism moved the metric; one good dot is not proof.

    Protocol deep dive

    Verification closes the gap between 'works in directed test' and 'legal under all stressed traffic'.

    Concept diagram

    Diagram
    VERIFICATION CLOSURE LOOP
    
    spec clause -> test -> assertion -> coverage -> waiver -> signoff
                      ^                           |
                      +--------- gap found --------+

    Metric graph

    Diagram
    COVERAGE vs ESCAPE RATE
    
    escapes
      |*
      | *
      |  *
      |   **  <- knee: more random helps
      |     ****
      +----------------> constrained-random depth

    Metrics and artifacts to collect

    • compliance pass rate

    • coverage closure

    • scoreboard mismatch rate

    • assertion fire count

    • waiver log

    Mini case study

    Block passed VIP compliance but chip failed: system test omitted cross-master ID reuse through a bridge. Scoreboard key did not include upstream port ID.

    Debug branches

    • If VIP pass but silicon fail, check integration assumptions.

    • If scoreboard noisy, fix key (ID+port+addr).

    • If coverage plateau, add compliance gap analysis not more repeats.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    Narrative walkthrough

    A team sees false fail rate, escaped bug count, response match latency drop 40% after a seemingly small change near Scoreboard & Checker Strategy.

    They almost widen the interface. Instead they capture id=7 read burst and find W beats never matched AW len.

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    See also

    • Scoreboard & Checker Strategy: Mechanism
    • Scoreboard & Checker Strategy: Inputs & Outputs
    • Scoreboard & Checker Strategy: Reports & Metrics