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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
    • VIP & Agent Architecture
    • Scoreboard & Checker Strategy
      • Scoreboard & Checker Strategy: Mechanism
      • Scoreboard & Checker Strategy: Inputs & Outputs
      • Scoreboard & Checker Strategy: Reports & Metrics
      • Scoreboard & Checker Strategy: Debug Playbook
      • Scoreboard & Checker Strategy: Worked Example
      • Scoreboard & Checker Strategy: Pitfalls & Red Flags
      • Scoreboard & Checker Strategy: Interview Drills
      • Scoreboard & Checker Strategy: Review Checklist
      • Scoreboard & Checker Strategy: Theory Deep Dive
      • Scoreboard & Checker Strategy: Design Space
      • Scoreboard & Checker Strategy: Expanded Case Study
      • Scoreboard & Checker Strategy: Step-by-Step Walkthrough
      • Scoreboard & Checker Strategy: Comparison Matrix
      • Scoreboard & Checker Strategy: Software / Programmer View
      • Scoreboard & Checker Strategy: Silicon PPA Impact
    • Compliance & Coverage Plan
    • Protocol Waveform Debug
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Scoreboard & Checker Strategy
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. Scoreboard & Checker Strategy
  5. Scoreboard & Checker Strategy: Step-by-Step Walkthrough

Interface Protocols · All levels

Scoreboard & Checker Strategy: Step-by-Step Walkthrough

Step-by-Step Walkthrough for Scoreboard & Checker Strategy.

On this page

    Step-by-step analysis walkthrough

    Follow this when you own Scoreboard & Checker Strategy in a protocol review or bring-up war room.

    1. State expected transaction in plain language (who initiates, what completes).

    2. Draw layer stack and mark clock/reset boundaries.

    3. List channels: request, data, response, snoop, credit, or lane.

    4. Tag ID/address/endpoint on the failing run.

    5. Find first cycle where progress stops or semantics change.

    6. Check bridge: width, ID remap, burst, ordering attributes.

    7. Check flow control: ready, credit, FIFO, link state.

    8. Check firmware/register mode vs hardware capability.

    9. Build minimal replay; confirm legal vs illegal per spec.

    10. Estimate metric delta from proposed fix.

    11. Run compliance + product traffic regression matrix.

    12. Write signoff memo with owners and artifacts attached.

    Artifacts to collect

    • scoreboard key map, assertion failure waveform, expected/actual transaction diff

    • VIP transaction log

    • Waveform with annotations

    • Spec clause reference

    • Regression manifest

    Decision memo template

    Diagram
    PROTOCOL DECISION MEMO — Scoreboard & Checker Strategy
    metric:
    transaction id:
    layer:
    hypothesis:
    experiment:
    fix:
    validation:
    owners: verification owner, formal owner, RTL owner

    Reference visuals

    Scoreboard correlation

    Diagram
    SCOREBOARD = MATCH REQUEST TO RESPONSE
    
    inbound req  : key = {id, addr}
    outbound resp: key = {id}
            |
            v
      map[key] = expected ; on response compare actual
            |
       mismatch -> log first failing key + timestamp (not the 100th)
    
    Assertions catch LOCAL rules; scoreboards catch END-TO-END correctness.

    Protocol deep dive

    Verification closes the gap between 'works in directed test' and 'legal under all stressed traffic'.

    Concept diagram

    Diagram
    VERIFICATION CLOSURE LOOP
    
    spec clause -> test -> assertion -> coverage -> waiver -> signoff
                      ^                           |
                      +--------- gap found --------+

    Metric graph

    Diagram
    COVERAGE vs ESCAPE RATE
    
    escapes
      |*
      | *
      |  *
      |   **  <- knee: more random helps
      |     ****
      +----------------> constrained-random depth

    Metrics and artifacts to collect

    • compliance pass rate

    • coverage closure

    • scoreboard mismatch rate

    • assertion fire count

    • waiver log

    Mini case study

    Block passed VIP compliance but chip failed: system test omitted cross-master ID reuse through a bridge. Scoreboard key did not include upstream port ID.

    Debug branches

    • If VIP pass but silicon fail, check integration assumptions.

    • If scoreboard noisy, fix key (ID+port+addr).

    • If coverage plateau, add compliance gap analysis not more repeats.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    Principal review addendum

    Re-read Scoreboard & Checker Strategy against one concrete product workload, not a synthetic directed test.

    scoreboards correlate requests and responses while assertions check local temporal rules and illegal combinations.

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    See also

    • Scoreboard & Checker Strategy: Mechanism
    • Scoreboard & Checker Strategy: Inputs & Outputs
    • Scoreboard & Checker Strategy: Reports & Metrics