The control SRAM returns corrected data at its normal response point and records the first failing address and syndrome. An uncorrectable read never masquerades as normal data; the surrounding transaction receives the block's documented poison or error response.

Correction and reporting occur together. Software may need the failing address and syndrome, but the capture register must define first-error versus last-error behavior and avoid being overwritten before service.

Carry the accepted request address/tag alongside the protected word through every memory/decode stage. Define a response-aligned event {valid, addr, syndrome, ce, ue} at decode completion, one event per decoded read, independently of downstream response stalls. A held response must not increment counters repeatedly. The diagnostic capture below consumes that event; it never samples the current request address.

Read the picture from the top: the address of read A never comes from the request port again. It rides beside the data until the decoder reports it.

• One event per decoded read. A stalled response does not repeat the event, so counters count reads, not stall cycles.

• The right address. By the time A is decoded, the port may hold request C; the event still says A.

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// snippet: response-aligned status capture; inside clocked logic
if (ecc_event.valid && ecc_event.ce)
  ce_count_q <= &ce_count_q ? ce_count_q : ce_count_q + 1'b1;
if (ecc_event.valid && (ecc_event.ce || ecc_event.ue) && !first_error_valid_q) begin
  first_error_valid_q <= 1'b1;
  first_error_addr_q  <= ecc_event.addr;
  first_syndrome_q    <= ecc_event.syndrome;
end
if (ecc_event.valid && ecc_event.ue) fatal_error_q <= 1'b1;

Related topics

• Partial writes and scrubbing