Ten weeks after decision C, four things change in the same week. This round tests whether the first decision was recorded well enough to revisit piece by piece instead of starting over.
Change | From | To |
|---|---|---|
Power budget for the block | baseline | 20% lower |
Camera | resolution undecided | confirmed at 2×: 3.2 GB/s peak, same 256-byte bursts |
Schedule | baseline | 3 weeks shorter |
Security | undecided | crypto keys must never be visible on a shared path |
Security confirms the deciding constraint. C was chosen to survive exactly this answer. The irreversible part of the decision holds; A is now ruled out for good. Record it and move on.
The camera doubling was a named review trigger. Re-run the numbers it touches: peak demand 3.2 + 0.8 = 4.0 GB/s, 63% of 6.4 GB/s. Bursts stay 256 bytes, so audio still waits at most 80 ns. Nothing reopens.
Power is new. It needs a plan, and it interacts with the fabric clock, which the record lists as a review trigger.
Schedule is new. Three weeks must come from somewhere; the record says which choices are cheap to change and which are not.
Dynamic power scales with clock frequency at a fixed voltage. Lowering the fabric clock from 800 MHz to 640 MHz cuts dynamic power by 1 − 640/800 = 20%, exactly the new budget, if leakage is small for this block (an assumption for the power lead to confirm). The cost is bandwidth: 8 bytes × 640 MHz = 5.12 GB/s, so the 4.0 GB/s peak becomes 78% utilisation. That is below the 80% ceiling the SoC architect uses for shared fabrics, but with little margin.
Latency must be rechecked, because it depends on the clock: a 32-beat burst at 640 MHz takes 32 / 640 MHz = 50 ns, and audio's worst wait becomes 100 ns, still far inside 2 µs.
A second, cheaper lever comes first: clock-gate each channel when its ring is empty, so the crypto channel and the shared engine burn little power between bursts. Present both: gating as the default, the 640 MHz clock as the fallback if gating alone does not reach 20%, with the 78% utilisation stated as its risk.
Candidate cut | Saves | Cost | Decision |
|---|---|---|---|
Descriptor chaining for audio (use a simple ring) | about 1 week of design and test | Firmware handles audio with a fixed ring | Cut |
Programmable QoS weights (keep fixed round-robin) | about 1 week | Weights cannot be tuned in the field; latency proof above uses round-robin anyway | Cut, with a register reserved for later |
Error injection tests on the secure channel | about 1 week | The one path security just made mandatory goes untested | Keep |
CDC and reset verification of the new fabric port | about 1 week | The failures that escape to silicon are the expensive ones | Keep |
Performance counters | a few days | Harder bring-up and tuning | Keep, if gating is the power plan, to prove it works |
The two cuts come from features whose absence is reversible or invisible to the requirements. The protected items are the ones security and silicon risk depend on. Write the cuts into the decision record with the person who accepted each one.
Field | Update |
|---|---|
Decision | C holds |
Closed | Crypto isolation (physical path required); camera at 2× verified against bandwidth and latency |
New | Power: channel clock gating first; fabric at 640 MHz as fallback (78% utilisation, 100 ns worst audio wait) |
Cuts (accepted by) | Audio descriptor chaining (audio lead); programmable QoS weights (SoC architect) |
New assumptions (owner) | Leakage small enough that frequency sets power (power lead); 80% utilisation ceiling (SoC architect) |
Review triggers | Gating misses the power target; any request for bursts over 256 bytes; fabric clock below 640 MHz |
The record already names the fallback: move the fabric to 640 MHz. Before doing so, confirm the 78% utilisation is acceptable to the SoC architect and recheck latency at the new clock (100 ns worst case). If 78% is rejected, the conversation becomes a budget negotiation, with the numbers on the table: a smaller power cut, a wider fabric, or a lower camera rate.
Keep them. Reuse lowers the risk but does not remove it: the new port has its own clock relationship, reset and integration wiring, and CDC escapes are among the costliest to find in silicon. Offer a cheaper cut from the reversible list instead.
Because the first round chose the option that survives the strictest security answer and recorded security as the deciding constraint. When the strict answer arrived, it confirmed the basis of the decision. A review that had picked A to save area would now be redesigning.
Arithmetic only: 1 - 640/800 = 20% dynamic power at fixed voltage, 8 bytes x 640 MHz = 5.12 GB/s, 4.0 / 5.12 = 78% utilisation, 32 beats at 640 MHz = 50 ns. Leakage is assumed small; schedule savings are planning estimates. Nothing on this page was simulated.