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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
    • Low-Power RTL Hub
    • DFT and Scan Hub
    • Physical Awareness Hub
    • Waveform Debug Hub
    • STA and ECO Hub
    • RTL-to-Implementation Closure
    • DFT-Ready RTL
    • Capstone: Resilient Streaming Peripheral
    • Principal Design Review
    • Senior RTL Interview Questions & Model Answers
      • Interview: Combinational and Arithmetic
      • Interview: Sequential and Pipelines
      • Interview: FSM and Control
      • Interview: Timing and STA
      • Interview: CDC and Reset
      • Interview: Memories and Buses
      • Interview: Low-Power Design
      • Interview: Debug and ECO
        • X-propagation discipline
        • Why simulation and silicon disagree
        • Capturing an intermittent failure
        • ECO or RTL change
      • Interview: Coding and Whiteboard
  • Glossary and Notation
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‹Interview: Debug and ECO
  1. Topics
  2. RTL Design
  3. Senior & Interview
  4. Senior RTL Interview Questions & Model Answers
  5. Interview: Debug and ECO
  6. ECO or RTL change

Part 9 · Senior · Senior

ECO or RTL change

When a late timing fix is a gate-level ECO and when it needs an RTL change, with a decision table.

On this page

    Why this matters

    A week before tape-out, an unneeded RTL rewrite can miss the window and a stacked gate ECO can break hold. The interviewer asks to see risk judgment: locality against fragility.

    After this lesson you can: decide between a gate-level ECO and an RTL change from the failure's locality, and say what evidence closes an ECO.

    The question

    The interviewer describes one red path a week before tape-out and asks for a gate-level ECO or an RTL change. The question tests risk judgment under schedule pressure. The answer weighs locality against fragility.

    Model answer

    Check the constraint first. A wrong clock definition makes STA report a violation the hardware never sees, and no design change fixes that.

    Then classify by locality. A single failing path takes a local gate edit; a structural shortfall repeated across many paths takes an RTL change. Repeated ECOs on the same logic are the signal that the structure is wrong.

    Decision flow. If the constraint is wrong, fix it and rerun STA. If it is correct and the failure is local, try a gate-level ECO. If the ECO leaves all views clean with nothing new nearby, close with equivalence, regressions and all views; otherwise escalate to an RTL change. A non-local failure goes straight to an RTL change.
    The ECO-or-RTL decision: check the constraint, classify by locality, and escalate to RTL when local edits stop converging.

    Start at the top. The arrow from the ECO check back to the RTL change is the escalation rule.

    • The constraint check comes first because no design change can fix a wrong constraint.

    • Locality decides the first attempt, not the final answer.

    • An ECO that breaks hold or creates nearby violations sends you to RTL instead of another edit.

    Symptom

    Gate-level ECO

    RTL change

    One setup path misses by a small margin

    Resize or buffer cells on that path

    Not needed

    A few hold violations

    Add delay cells on those paths

    Rarely needed for hold

    Violations spread across many paths

    Each edit risks new damage

    Restructure the logic or add a pipeline stage

    A wrong or missing constraint

    Fix the constraint and re-run STA

    No design change

    A functional bug found late

    A functional ECO can patch logic using available cells and permitted routing/masks; size and physical feasibility limit it

    Correct the golden RTL/specification and verify the patched implementation against that intended behavior

    Interview

    Strongest one-line answer: a local failure takes a gate edit, a structural failure takes RTL, and repeated ECOs mean the structure is wrong.

    Follow-ups

    • The fix needs a new flop. Can an ECO do it? Only if a spare flop (or spare cells that can form one) sits near the logic. A metal-only ECO rewires pre-placed spares; a base-layer change costs new masks. The new flop must be stitched into scan or explicitly excluded, and equivalence checking must still match the corrected RTL.

    • The ECO fixes setup but breaks hold on the same path. What now? The path has no room for a local edit. That fragility is the escalation signal: take the RTL change instead of stacking edits.

    • What evidence closes an ECO? Formal equivalence to the intended golden RTL, affected functional regressions, all required setup/hold views and physical checks. A timing-only ECO preserves function; a functional ECO implements the documented corrected behavior. Neither simulation alone nor clean timing proves the patch correct.

    Common wrong answers

    • “ECO is always cheaper.” A gate edit is cheaper only while it stays local. Stacked edits interact, and each one re-opens verification.

    • “Restructure the RTL; it is cleaner.” Cleanliness is not the metric a week before tape-out. A localized, verified ECO beats a correct-looking rewrite that misses the window.

    Common pitfall

    Fixing setup while ignoring hold. Every ECO needs both reports clean, or the fix trades one violation for another.

    Check yourself Three ECO iterations have touched the same block and STA still shows new violations nearby. What is the call?

    Stop editing gates and change the RTL. Nearby new violations mean the edits are disturbing shared logic; the structure cannot absorb a local fix.

    Check yourself The violation disappears when the constraint is corrected. What shipped?

    Nothing. The hardware was never broken; the check was. Re-run full STA on the corrected constraints as the closing evidence.

    Remember

    • Check the constraint first. A wrong clock definition gives a violation the hardware never sees.

    • A single failing path takes a local gate edit. A structural shortfall across many paths takes an RTL change.

    • Fix setup and hold together, and close an ECO with equivalence, regressions and all timing views.

    Rule of thumb: repeated ECOs on the same logic mean the structure is wrong.

    Keep going

    • Interview: run a mock interview on this topic

    Related topics

    • RTL patterns for timing

    • Fix strategy: setup vs hold

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    See also

    • X-propagation discipline
    • Why simulation and silicon disagree