The interviewer asks where to look first when the testbench passes and the chip fails. The question tests for a systematic search, not a guess. The answer is a taxonomy ordered by how often each gap bites.
Every gap below shares one shape: the simulator models an idealization that silicon does not honor. The fix is to name the idealization and add the check that removes it.
Answer the questions from the top; each yes sends you to one family of gaps in the table.
The questions are cheap to answer in the lab: vary the supply, power-cycle the part, and note which interface misbehaves.
Each end box names a row of the table and the check that removes that idealization.
A failure can have more than one cause. Starting in the right family only shortens the search.
Gap | Why simulation passes | What silicon does | How to catch it |
|---|---|---|---|
Uninitialized state (X-optimism) | An X takes a benign branch, as in the previous lesson | Powers up 0 or 1, arbitrarily | X-propagation runs plus reset discipline |
Races in clocked logic | Blocking assignments evaluate in a benign order | Fixed hardware with no ordering choice | Nonblocking rule for |
Missing or wrong constraints | STA checks a clock that was never real | Violates setup or hold on the true clocks | Constraint review against the real clocking, report-driven sign-off |
Clock-domain crossings | Transfers look clean in RTL simulation | Metastability on unsynchronized crossings | Synchronizer plus protocol review on every crossing |
Power intent absent from simulation | Isolation and retention behave as plain wires | Clamps, floats, or loses state | Power-aware simulation and clamp checks |
Untested corners and modes | Typical corner and mission mode pass | Fails slow, fast, low-voltage, or scan-mode corners | Corner STA and scan-mode timing checks |
The failure appears only at low voltage. What changes? Timing margins shrink and marginal paths fail first. The fix is corner STA and characterization coverage, not more typical-corner simulation.
STA is clean and the lab failure looks like a protocol violation. What now? Constraints may describe a clock that the board does not provide, or CDC paths may lack synchronizers. Review constraints against the real clocking and audit every crossing.
“Run more random seeds.” Random stimulus exercises the same idealizations. A gap in the model never closes by sampling it more.
“It must be a tool bug.” Tool bugs exist but are rare. Model gaps outnumber them by far, so audit the model first.
A wrong constraint on that clock, or an unconstrained CDC path feeding the interface. Both make STA check something other than the real hardware.
Power intent and analog effects. Sims without power intent still idealize isolation and retention, and no digital sim covers signal integrity.