The question

The interviewer asks what causes X-propagation and what keeps unknowns out of sign-off simulation. The question tests whether reset discipline is a habit or a slogan.

Model answer

Unknowns come from uninitialized flops, incomplete reset, memories with no defined contents, and powered-down domains driving live logic.

Simulation resolves some X cases optimistically. An if with an X select takes the else branch, and a case with no matching branch holds its old value.

A ternary with disagreeing inputs yields X instead. Silicon resolves every unknown to 0 or 1, so optimism hides bugs that the chip then shows.

Each row is one step of the testbench further down, in the same order; the outputs are what the simulation printed for that step.

• Rows 1 and 2 are ordinary: all three codings agree on a known select.

• Row 3 is the trap. Only the ternary reports X; the if/else and the case each show a clean value that silicon need not produce.

• Row 4: the ternary resolves to 1 because both inputs agree, while the case still shows the stale 0 from row 2.

An RTL X represents digital uncertainty; it is not an analog metastability model. Four-state tests cannot establish synchronizer settling margin or MTBF. Physical CDC closure still needs the canonical synchronizer/protocol review and implemented timing evidence.

The discipline has three parts: reset every flop that affects behavior or prove the value unreachable, give memories defined contents or model the unknown explicitly, and clamp or isolate powered-off outputs.

Solution and testbench

One module shows all three codings side by side, with a testbench that drives 0, 1, and X through the select.

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`timescale 1ns/1ps
module x_pessimism (
  input wire sel,
  input wire a,
  input wire b,
  output reg y_if,
  output reg y_case,
  output wire y_mux
);
  always @* begin
    if (sel) y_if = a;
    else y_if = b;
  end
  always @* begin
    // Binary-complete: X/Z retention in simulation does not establish a synthesized latch.
    case (sel)
      1'b0: y_case = b;
      1'b1: y_case = a;
    endcase
  end
  assign y_mux = sel ? a : b;
endmodule

Each of the four stimulus steps checks all three outputs. Under X with disagreeing inputs, the if/else takes the else branch, the case holds its old value, and the ternary yields X.

The one-bit case covers both binary values. Its four-state X/Z retention is a simulation semantic, not a physical latch. In contrast, the following snippet leaves sel=0 unassigned, so even a legal binary input requires prior state.

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// snippet: genuinely missing binary assignment, unlike the case above.
always @* begin
  case (sel)
    1'b1: y_incomplete = a;
    // sel=0 has no assignment: storage is required to retain y_incomplete.
  endcase
end

Follow-ups

• Why does the ternary yield X only when the inputs disagree? The operator resolves to the common value when both sides agree. Disagreement with an unknown select leaves no safe choice, so the result is X.

• How do X sources get found in a large design? Run X-propagation simulation modes, trace each X to reset, init, or power intent, and close them one by one.

• When is X in simulation acceptable? When the value is provably unreachable, such as a debug bus sampled only in a mode the design never enters. Document the proof rather than relying on optimism.

Common wrong answers

• “X means do not care, so it does not matter.” An X in RTL simulation means unknown, not do not care. Silicon resolves it to a real value that the testbench never checked.

• “Reset everything and the problem is solved.” Full reset costs routing, power, and timing on every flop. Reset what matters and prove the rest unreachable.

Related topics

• The complete-assignment pattern

• Mux theory and design patterns